On Thu, Sep 03, 2020 at 10:27:12PM +0200, Marek Vasut wrote:
> The phy_reset_after_clk_enable() does a PHY reset, which means the PHY
> loses its register settings. The fec_enet_mii_probe() starts the PHY
> and does the necessary calls to configure the PHY via PHY framework,
> and loads the correct register settings into the PHY. Therefore,
> fec_enet_mii_probe() should be called only after the PHY has been
> reset, not before as it is now.
I think this patch is related to what Florian is currently doing with
PHY clocks.
I think a better fix for the original problem is for the SMSC PHY
driver to control the clock itself. If it clk_prepare_enables() the
clock, it knows it will not be shut off again by the FEC run time
power management.
All this phy_reset_after_clk_enable() can then go away.
Andrew
