On Sun, Aug 18, 2019 at 09:25:58PM +0300, Vladimir Oltean wrote: > On platforms like LS1021A which use TCFQ mode, an interrupt needs to be > processed after each byte is TXed/RXed. I tried to make the DSPI > implementation on this SoC operate in other, more efficient modes (EOQ, > DMA) but it looks like it simply isn't possible.
This doesn't apply against current code (I guess due to your cleanup series), please check and resend.
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