On Mon, 22 Apr 2019 19:46:47 -0700
Jakub Kicinski <jakub.kicin...@netronome.com> wrote:
> On Mon, 22 Apr 2019 15:32:53 -0700, Saeed Mahameed wrote:
> > diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h
> > b/drivers/net/ethernet/mellanox/mlx5/core/en.h
> > index 51e109fdeec1..6147be23a9b9 100644
> > --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
> > +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
> > @@ -50,6 +50,7 @@
> > #include <net/xdp.h>
> > #include <linux/net_dim.h>
> > #include <linux/bits.h>
> > +#include <linux/prefetch.h>
> > #include "wq.h"
> > #include "mlx5_core.h"
> > #include "en_stats.h"
> > @@ -986,6 +987,22 @@ static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
> > mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
> > }
> >
> > +static inline void mlx5e_prefetch(void *p)
> > +{
> > + prefetch(p);
> > +#if L1_CACHE_BYTES < 128
> > + prefetch(p + L1_CACHE_BYTES);
> > +#endif
> > +}
> > +
> > +static inline void mlx5e_prefetchw(void *p)
> > +{
> > + prefetchw(p);
> > +#if L1_CACHE_BYTES < 128
> > + prefetchw(p + L1_CACHE_BYTES);
> > +#endif
> > +}
>
> All Intel drivers do the exact same thing, perhaps it's time to add a
> helper fot this?
>
> net_prefetch_headers()
>
> or some such?
I wonder if Tariq measured any effect from doing this?
Because Intel CPUs will usually already prefetch the next cache-line,
as described in [1], you can even read (and modify) this MSR 0x1A4
e.g. via tools in [2]. Maybe Intel guys added it before this was done
in HW, and never cleaned it up?
[1]
https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors
--
Best regards,
Jesper Dangaard Brouer
MSc.CS, Principal Kernel Engineer at Red Hat
LinkedIn: http://www.linkedin.com/in/brouer
[2] http://www.kernel.org/pub/linux/utils/cpu/msr-tools/
