On 2/14/19 2:40 PM, Andrew Lunn wrote:
> On Thu, Feb 14, 2019 at 07:45:57AM +0100, Christophe Roullier wrote:
>> @@ -131,19 +185,19 @@ static int stm32mp1_set_mode(struct
>> plat_stmmacenet_data *plat_dat)
>> case PHY_INTERFACE_MODE_RGMII:
>> val = SYSCFG_PMCR_ETH_SEL_RGMII;
>> - if (dwmac->int_phyclk)
>> + if (dwmac->eth_clk_sel_reg)
>> val |= SYSCFG_PMCR_ETH_CLK_SEL;
>> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
>> break;
>
> Hi Christophe
>
> This code should handle all 4 PHY_INTERFACE_MODE_RGMII* values.
>
> Andrew
>
Hi Andrew,
For RGMII we are supporting 3 modes:
- normal mode (with PHY with quartz)
- Phy wo crystal and phy is clocking with PLL to 25Mhz.
- other mode where we used PLL from RCC (125Mhz) to clock Ethernet
IP (save one pin "ETH_CK125")
In driver source code I put table to sum-up all configs supported for
each phy mode:
+ * Below table summarizes the clock requirement and clock sources for
+ * supported phy interface modes.
+ *
__________________________________________________________________________
+ *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz
from PHY|
+ *| | | 25MHz | 50MHz |
|
+ *
---------------------------------------------------------------------------
+ *| MII | - | eth-ck | n/a | n/a |
+ *| | | | | |
+ *
---------------------------------------------------------------------------
+ *| GMII | - | eth-ck | n/a | n/a |
+ *| | | | | |
+ *
---------------------------------------------------------------------------
+ *| RGMII | - | eth-ck | n/a | eth-ck (no pin) |
+ *| | | | |
st,eth_clk_sel |
+ *
---------------------------------------------------------------------------
+ *| RMII | - | eth-ck | eth-ck | n/a |
+ *| | | | st,eth_ref_clk_sel | |
+ *
---------------------------------------------------------------------------
Regards,
Christophe
