From: Pankaj Bansal <pankaj.ban...@nxp.com> Date: Mon, 4 Feb 2019 08:51:57 +0000
> The two external MDIO buses used to communicate with phy devices that are > external to SOC are muxed in LX2160AQDS board. > > These buses can be routed to any one of the eight IO slots on LX2160AQDS > board depending on value in fpga register 0x54. > > Additionally the external MDIO1 is used to communicate to the onboard > RGMII phy devices. > > The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is > controlled by bits 0-3 of fpga register. > > Signed-off-by: Pankaj Bansal <pankaj.ban...@nxp.com> Am I applying this to my networking tree or are the ARM folks taking this?
