Hi Bhadram, Does the Tegra by any chance have TSO enabled on multiple TX-DMA channels ?
I recently noticed a second TSO bug in the stmmac while making the patch "stmmac: reset last TSO segment size after device open". The last-used MSS setting in TSO is tracked as a device-global variable and not per TX queue. Using TSO on tx queue 0 will record mss to priv->mss and if we later use TSO on tx queue 1 with the same gso_size then the driver will not use a context descriptor to set the MSS size for this queue. This probably means that the TSO controller in channel 1 goes nuts with an undefined mss setting. BR, Lars Persson On Mon, Nov 20, 2017 at 7:38 AM, Bhadram Varka <vbhad...@nvidia.com> wrote: > Hi Joao/Peppe, > > Observed this issue more frequently with multi-channel case. Am I missing > something in DT ? > Please help here to understand the issue. > > Thanks, > Bhadram > > -----Original Message----- > From: Bhadram Varka > Sent: Thursday, November 16, 2017 9:41 AM > To: linux-netdev <netdev@vger.kernel.org> > Subject: NETDEV WATCHDOG: eth0 (dwc-eth-dwmac): transmit queue 1 timed out > > Hi, > > I am trying to enable multi-queue in Tegra186 EQOS (which has support for 4 > channels). Observed below netdev watchdog warning. Its easily reproable with > iperf test. > In normal ping scenario this is not observed. I did not observe any issue if > we disable TSO. Looks like issue in stmmac_tso_xmit() in multi-channel > scenario. >
