Hi Andrew,
thanks for the suggestion
On Thu, Oct 05, 2017 at 06:48:26PM +0200, Andrew Lunn wrote:
> On Thu, Oct 05, 2017 at 05:42:39PM +0200, jacopo mondi wrote:
> > Hi Andrew,
[snip]
> > > Hi Jocopo
> > >
> > > So what is this reset resetting?
> > >
> > > The MAC?
> > > The PHY?
> >
> > The reset line goes from our SoC to LAN8710A PHY chip external reset pin.
>
> So yes, this is a PHY property, and should be in the PHY node.
>
> Documentation/devicetree/bindings/net/mdio.txt does not apply here
> anyway. That is for an MDIO binding. This node is an ethernet MAC.
>
> So your binding whats to look something like
>
> ether: ethernet@e8203000 {
> compatible = "renesas,ether-r7s72100";
> reg = <0xe8203000 0x800>,
> <0xe8204800 0x200>;
> interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
> power-domains = <&cpg_clocks>;
> phy-mode = "mii";
> phy-handle = <&phy0>;
> #address-cells = <1>;
> #size-cells = <0>;
>
> mdio: bus-bus {
> #address-cells = <1>;
> #size-cells = <0>;
>
> phy0: ethernet-phy@1 {
> reg = <1>;
Why reg = <1> ?
Shouldn't this be 0, or even better with no reg property at all?
mdio: bus-bus {
phy-0 {
reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <5>;
};
};
Thanks
j
> reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> reset-delay-us = <5>;
> };
> };
> };
>
> Andrew
