Hi Andrew, On Thu, Oct 05, 2017 at 03:43:39PM +0200, Andrew Lunn wrote: > On Thu, Oct 05, 2017 at 11:39:15AM +0200, jacopo mondi wrote: > > Hi Geert > > > > On Thu, Oct 05, 2017 at 11:09:40AM +0200, Geert Uytterhoeven wrote: > > > Hi Jacopo, > > > > > > On Thu, Oct 5, 2017 at 10:58 AM, Jacopo Mondi <jacopo+rene...@jmondi.org> > > > wrote: > > > > Add pin configuration subnode for ETHER pin group and enable the > > > > interface. > > > > > > > > Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org> > > > > > > Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be> > > > > > > > --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts > > > > +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts > > > > > > > @@ -88,3 +110,19 @@ > > > > > > > > status = "okay"; > > > > }; > > > > + > > > > +ðer { > > > > + pinctrl-names = "default"; > > > > + pinctrl-0 = <ðer_pins>; > > > > + > > > > + status = "okay"; > > > > + > > > > + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; > > > > + reset-delay-us = <5>; > > > > > > I'm afraid the PHY people (not CCed ;-) will want you to move these reset > > > properties to the phy subnode these days, despite > > > Documentation/devicetree/bindings/net/mdio.txt... > > Hi Jocopo > > So what is this reset resetting? > > The MAC? > The PHY?
The reset line goes from our SoC to LAN8710A PHY chip external reset pin. Thanks j > > Andrew