> > My concern is if a task is already running with SPI access to a lot > > of registers like reading the 32 MIB counters in every port of the > > switch, another register access has to wait until they are finished. > > Why does it have to wait? Looking at the code in > ksz_get_ethtool_stats(), you don't take any mutex which will prevent > others from using the SPI bus. All there is is a mutex which prevents > two sets of ksz_get_ethtool_stats() at the same time. > > So a PTP read could happen in parallel, and will not be blocked by MIB > reads. They should get interleaved access to the SPI bus. >
The MIB counters are read in the background. For multiple CPU cores 2 tasks may run in the same time allowing SPI access one after another. For single core I am not sure an SPI access like coming from an interrupt routine can jump ahead from one in a background task. I know nowadays SoCs are powerful enough to do amazing things. It is just I spent a long time using a low-powered SoC doing switch driver development.
