On 01/04/2017 10:18 PM, Sergei Shtylyov wrote:
As the SH77{34|63} manuals are freely available, I've checked the EESIPR
values written against the manuals, and they appeared to set the reserved
bits 11-15 (which should be 0 on write). Fix those EESIPR values.
Fixes: 380af9e390ec ("net: sh_eth: CPU dependency code collect to "struct
sh_eth_cpu_data"")
For SH7763 the bug is older than this commit but the code was common for
all SH SoCs supported back then and so couldn't be fixed w/o affecting other
SoCs. However, I suspect that the mask was incorrect even for the other SoCs...
Fixes: f5d12767c8fd ("sh_eth: get SH77{34|63} support out of #ifdef")
That's the point where SH7734/63 data were split...
Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
[...]
MBR, Sergei
