Às 6:21 PM de 12/21/2016, David Miller escreveu: > From: Joao Pinto <joao.pi...@synopsys.com> > Date: Tue, 20 Dec 2016 11:21:47 +0000 > >> When testing stmmac with my QoS reference design I checked a problem in the >> CSR clock configuration that was impossibilitating the phy discovery, since >> every read operation returned 0x0000ffff. This patch fixes the issue. >> >> Signed-off-by: Joao Pinto <jpi...@synopsys.com> > > This isn't enough. > > It looks like various parts of this driver set the mask field > differently. > > dwmac1000_core.c and dwmac100_core.c set the mask to be the low bits. > > But dwmac4_core.c uses GENMASK(11, 8) which means the mask is a value > which is shifted up already. > > So your patch will break chips driven by dwmac4_core.c.
I am using a GMAC4 reference design to test the patches. The clock configuration as is, does not work, resulting in the phy discovery failure. By applying this patch I am able to set the clock value properly. I am going to check in the Databook of GMAC4 and older versions in order to justify better. > > In order for your change to be correct you must consolidate all of > these various pieces to use the same convention. > Thanks.
