Hi All, On Sat, Jan 28, 2012 at 12:32 AM, Joel jaeggli <joe...@bogus.com> wrote: > On 1/27/12 14:53 , bas wrote: >> While I agree _again_!!!!! >> >> It does not explain why TOR boxes have little buffers and chassis box >> have many..... > > you need purportionally more buffer when you need to drain 16 x 10 gig > into 4 x 10Gig then when you're trying to drain 10Gb/s into 2 x 1Gb/s > > there's a big incentive bom wise to not use offchip dram buffer in a > merchant silicon single chip switch vs something that's more complex.
I'm almost ready to throw the towel in the ring, and declare myself a looney.. I can imagine at least one vendor ingnoring the extra BOM capex, and simpky try to please #$%^#@! like me. C NSP has been full with threads about appalling microburst performance of the 6500 for years.. One would think a vendor would jump to a copetitive edge like this...
