> On Sep 29, 2023, at 15:14, William Herrin <b...@herrin.us> wrote: > > On Fri, Sep 29, 2023 at 3:11 PM Owen DeLong <o...@delong.com> wrote: >> You continue to assume that there is a fast SRAM cache. I’m not sure >> that is true. I think that all of the FIB RAM on the line cards is fast SRAM >> and no cache. > > Hi Owen, > > I'm less assuming it and more reading it from this SIGCOMM paper: > https://people.csail.mit.edu/ghobadi/papers/trio_sigcomm_2022.pdf Fair enough, but interestingly, I think that the compiled line-card forwarding table probably always fits in the cache. Owen
- Re: maximum ipv4 bgp prefix length of /24 ? Owen DeLong via NANOG
- Re: maximum ipv4 bgp prefix length of /24 ? William Herrin
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- Re: maximum ipv4 bgp prefix length of /24 ? William Herrin
- Re: maximum ipv4 bgp prefix length of /24 ? Tom Beecher
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- Re: maximum ipv4 bgp prefix length of /24 ? William Herrin
- Re: maximum ipv4 bgp prefix length of /24 ? Owen DeLong via NANOG
- Re: maximum ipv4 bgp prefix length of /24 ? William Herrin
- Re: maximum ipv4 bgp prefix length of /24 ? Tom Beecher
- Re: maximum ipv4 bgp prefix length of /24 ? Owen DeLong via NANOG
- Re: maximum ipv4 bgp prefix length of /24 ? William Herrin
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- Re: maximum ipv4 bgp prefix length of /24 ? Owen DeLong via NANOG
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- Re: maximum ipv4 bgp prefix length of /24 ? Owen DeLong via NANOG