On 04.11.2015 10:10, Michel Dänzer wrote:
On 04.11.2015 18:06, Christian König wrote:
On 04.11.2015 09:54, Michel Dänzer wrote:
@@ -188,8 +191,11 @@ static uint64_t radeon_bomgr_find_va(struct
radeon_bomgr *mgr, uint64_t size, ui
struct radeon_bo_va_hole *hole, *n;
uint64_t offset = 0, waste = 0;
+ /* Start of VM address range only needs to be aligned to the
GPU page
+ * size, which is always 4K
+ */
alignment = MAX2(alignment, 4096);
- size = align(size, 4096);
+ size = align(size, mgr->size_align);
Since all allocations are round up to the CPU page size it probably
doesn't matter, but we might want to adjust the alignment as well.
As the comment says, AFAIK the GPUVM base address only needs to be
aligned to the GPU page size. If it must be aligned to the CPU page size
as well, where does that requirement come from?
As I wrote when all sizes are aligned to the CPU page size all your base
addresses are aligned as well, because you don't get holes smaller than
the page size.
The patch is Reviewed-by: Christian König <christian.koe...@amd.com>
anyway, I just thought that it would make things more obvious.
Regards,
Christian.
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