On Tue, Nov 3, 2015 at 10:21 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> On Wednesday, October 21, 2015 03:58:16 PM Matt Turner wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_eu_validate.c | 257
>> ++++++++++++++++++++++++++++
>> 1 file changed, 257 insertions(+)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c
>> b/src/mesa/drivers/dri/i965/brw_eu_validate.c
>> index 85d4c19..eb57962 100644
>> --- a/src/mesa/drivers/dri/i965/brw_eu_validate.c
>> +++ b/src/mesa/drivers/dri/i965/brw_eu_validate.c
>> @@ -68,6 +68,234 @@ src1_is_null(const struct brw_device_info *devinfo,
>> const brw_inst *inst)
>> brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
>> }
>>
>> +enum gen {
>> + GEN4 = (1 << 0),
>> + GEN45 = (1 << 1),
>> + GEN5 = (1 << 2),
>> + GEN6 = (1 << 3),
>> + GEN7 = (1 << 4),
>> + GEN75 = (1 << 5),
>> + GEN8 = (1 << 6),
>> + GEN9 = (1 << 7),
>> + GEN_ALL = ~0
>> +};
>> +
>> +#define GEN_GE(gen) (~((gen) - 1) | gen)
>> +#define GEN_LE(gen) (((gen) - 1) | gen)
>
> Very nice! This works quite well.
I thought so! It has the nice benefit that if you forget to handle an
instruction in the table, it'll automatically be initialized to 0 (or,
supported no where :)
>> +
>> +struct inst_info {
>> + enum gen gen;
>> +};
>> +
>> +static const struct inst_info inst_info[128] = {
>> + [BRW_OPCODE_ILLEGAL] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_MOV] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_SEL] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_MOVI] = {
>> + .gen = GEN_GE(GEN45),
>> + },
>> + [BRW_OPCODE_NOT] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_AND] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_OR] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_XOR] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_SHR] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_SHL] = {
>> + .gen = GEN_ALL,
>> + },
>> + /* BRW_OPCODE_DIM / BRW_OPCODE_SMOV */
>> + /* Reserved - 11 */
>> + [BRW_OPCODE_ASR] = {
>> + .gen = GEN_ALL,
>> + },
>> + /* Reserved - 13-15 */
>> + [BRW_OPCODE_CMP] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_CMPN] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_CSEL] = {
>> + .gen = GEN_GE(GEN8),
>> + },
>> + [BRW_OPCODE_F32TO16] = {
>> + .gen = GEN7 | GEN75,
>> + },
>> + [BRW_OPCODE_F16TO32] = {
>> + .gen = GEN7 | GEN75,
>> + },
>> + /* Reserved - 21-22 */
>> + [BRW_OPCODE_BFREV] = {
>> + .gen = GEN_GE(GEN7),
>> + },
>> + [BRW_OPCODE_BFE] = {
>> + .gen = GEN_GE(GEN7),
>> + },
>> + [BRW_OPCODE_BFI1] = {
>> + .gen = GEN_GE(GEN7),
>> + },
>> + [BRW_OPCODE_BFI2] = {
>> + .gen = GEN_GE(GEN7),
>> + },
>> + /* Reserved - 27-31 */
>> + [BRW_OPCODE_JMPI] = {
>> + .gen = GEN_ALL,
>> + },
>> + /* BRW_OPCODE_BRD */
>> + [BRW_OPCODE_IF] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_IFF] = { /* also BRW_OPCODE_BRC */
>> + .gen = GEN_LE(GEN5),
>> + },
>> + [BRW_OPCODE_ELSE] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_ENDIF] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_DO] = { /* also BRW_OPCODE_CASE */
>> + .gen = GEN_LE(GEN5),
>> + },
>> + [BRW_OPCODE_WHILE] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_BREAK] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_CONTINUE] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_HALT] = {
>> + .gen = GEN_ALL,
>> + },
>> + /* BRW_OPCODE_CALLA */
>> + /* BRW_OPCODE_MSAVE / BRW_OPCODE_CALL */
>> + /* BRW_OPCODE_MREST / BRW_OPCODE_RET */
>> + /* BRW_OPCODE_PUSH / BRW_OPCODE_FORK / BRW_OPCODE_GOTO */
>> + /* BRW_OPCODE_POP */
>> + [BRW_OPCODE_WAIT] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_SEND] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_SENDC] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_SENDS] = {
>> + .gen = GEN_GE(GEN9),
>> + },
>> + [BRW_OPCODE_SENDSC] = {
>> + .gen = GEN_GE(GEN9),
>> + },
>> + /* Reserved 53-55 */
>> + [BRW_OPCODE_MATH] = {
>> + .gen = GEN_GE(GEN6),
>> + },
>> + /* Reserved 57-63 */
>> + [BRW_OPCODE_ADD] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_MUL] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_AVG] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_FRC] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_RNDU] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_RNDD] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_RNDE] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_RNDZ] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_MAC] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_MACH] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_LZD] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_FBH] = {
>> + .gen = GEN_GE(GEN7),
>> + },
>> + [BRW_OPCODE_FBL] = {
>> + .gen = GEN_GE(GEN7),
>> + },
>> + [BRW_OPCODE_CBIT] = {
>> + .gen = GEN_GE(GEN7),
>> + },
>> + [BRW_OPCODE_ADDC] = {
>> + .gen = GEN_GE(GEN7),
>> + },
>> + [BRW_OPCODE_SUBB] = {
>> + .gen = GEN_GE(GEN7),
>> + },
>> + [BRW_OPCODE_SAD2] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_SADA2] = {
>> + .gen = GEN_ALL,
>> + },
>> + /* Reserved 82-83 */
>> + [BRW_OPCODE_DP4] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_DPH] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_DP3] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_DP2] = {
>> + .gen = GEN_ALL,
>> + },
>> + /* Reserved 88 */
>> + [BRW_OPCODE_LINE] = {
>> + .gen = GEN_ALL,
>> + },
>> + [BRW_OPCODE_PLN] = {
>> + .gen = GEN_GE(GEN45),
>> + },
>> + [BRW_OPCODE_MAD] = {
>> + .gen = GEN_GE(GEN6),
>> + },
>> + [BRW_OPCODE_LRP] = {
>> + .gen = GEN_GE(GEN6),
>> + },
>> + /* Reserved 93-124 */
>> + /* BRW_OPCODE_NENOP */
>> + [BRW_OPCODE_NOP] = {
>> + .gen = GEN_ALL,
>> + },
>> +};
>> +
>> static unsigned
>> num_sources_from_inst(const struct brw_device_info *devinfo,
>> const brw_inst *inst)
>> @@ -81,6 +309,9 @@ num_sources_from_inst(const struct brw_device_info
>> *devinfo,
>> if (brw_inst_sfid(devinfo, inst) == BRW_SFID_MATH) {
>> math_function = brw_inst_math_msg_function(devinfo, inst);
>> } else {
>> + /* Send instructions are allowed to have null sources since they
>> use
>> + * the base_mrf field to specify which message register source.
>> + */
>
> Seems like this should go in the previous patch.
Whoops. Thanks!
> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Thanks!
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