On 09/10/2015 02:50 AM, Jason Ekstrand wrote:
> We made this switch in the FS backend some time ago and it seems to make a
> number of things a bit easier.
>
The commit log could be a bit less abstract, like mentioning why this
change helps the subsequent passes. In any case, if it was only for
consistency with FS, this change is beneficial.
I also tested it with full dEQP GLES3 suite, apart from piglit, on HWS.
No regressions.
Reviewed-by: Eduardo Lima Mitev <el...@igalia.com>
> ---
> src/mesa/drivers/dri/i965/brw_nir.c | 2 +-
> src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 ++++++++++++++++++---
> 3 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
> b/src/mesa/drivers/dri/i965/brw_nir.c
> index 8f3edc5..f326b23 100644
> --- a/src/mesa/drivers/dri/i965/brw_nir.c
> +++ b/src/mesa/drivers/dri/i965/brw_nir.c
> @@ -183,7 +183,7 @@ brw_create_nir(struct brw_context *brw,
> nir_print_shader(nir, stderr);
> }
>
> - nir_convert_from_ssa(nir, is_scalar);
> + nir_convert_from_ssa(nir, true);
> nir_validate_shader(nir);
>
> if (!is_scalar) {
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
> b/src/mesa/drivers/dri/i965/brw_vec4.h
> index 01c6e84..de74ec9 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
> @@ -423,6 +423,7 @@ public:
> virtual void nir_emit_alu(nir_alu_instr *instr);
> virtual void nir_emit_jump(nir_jump_instr *instr);
> virtual void nir_emit_texture(nir_tex_instr *instr);
> + virtual void nir_emit_undef(nir_ssa_undef_instr *instr);
>
> dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type);
> dst_reg get_nir_dest(nir_dest dest, nir_alu_type type);
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 751ec73..87a7941 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -367,6 +367,10 @@ vec4_visitor::nir_emit_instr(nir_instr *instr)
> nir_emit_texture(nir_instr_as_tex(instr));
> break;
>
> + case nir_instr_type_ssa_undef:
> + nir_emit_undef(nir_instr_as_ssa_undef(instr));
> + break;
> +
> default:
> fprintf(stderr, "VS instruction not yet implemented by NIR->vec4\n");
> break;
> @@ -393,9 +397,14 @@ dst_reg_for_nir_reg(vec4_visitor *v, nir_register
> *nir_reg,
> dst_reg
> vec4_visitor::get_nir_dest(nir_dest dest)
> {
> - assert(!dest.is_ssa);
> - return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
> - dest.reg.indirect);
> + if (dest.is_ssa) {
> + dst_reg dst = dst_reg(GRF, alloc.allocate(1));
> + nir_ssa_values[dest.ssa.index] = dst;
> + return dst;
> + } else {
> + return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
> + dest.reg.indirect);
> + }
> }
>
> dst_reg
> @@ -1528,4 +1537,10 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
> mcs, is_cube_array, sampler, sampler_reg);
> }
>
> +void
> +vec4_visitor::nir_emit_undef(nir_ssa_undef_instr *instr)
> +{
> + nir_ssa_values[instr->def.index] = dst_reg(GRF, alloc.allocate(1));
> +}
> +
> }
>
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