On Thursday, August 27, 2015 11:48:35 PM Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 3 +++
> src/mesa/drivers/dri/i965/brw_disasm.c | 1 +
> src/mesa/drivers/dri/i965/brw_fs.cpp | 7 +++++++
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4 ++++
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 1 +
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 +++
> src/mesa/drivers/dri/i965/brw_shader.cpp | 4 ++++
> src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 +
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 4 ++++
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 1 +
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10 +++++++++-
> 11 files changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index cb5c82a..d83ba50 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -978,6 +978,8 @@ enum opcode {
> SHADER_OPCODE_TG4_LOGICAL,
> SHADER_OPCODE_TG4_OFFSET,
> SHADER_OPCODE_TG4_OFFSET_LOGICAL,
> + SHADER_OPCODE_SAMPLEINFO,
> + SHADER_OPCODE_SAMPLEINFO_LOGICAL,
>
> /**
> * Combines multiple sources of size 1 into a larger virtual GRF.
> @@ -1510,6 +1512,7 @@ enum brw_message_target {
> #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
> #define GEN5_SAMPLER_MESSAGE_LOD 9
> #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
> +#define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
> #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
> #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
> #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 1075c5a..1453a59 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -601,6 +601,7 @@ static const char *const gen5_sampler_msg_type[] = {
> [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4] = "gather4",
> [GEN5_SAMPLER_MESSAGE_LOD] = "lod",
> [GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO] = "resinfo",
> + [GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO] = "sampleinfo",
> [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C] = "gather4_c",
> [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
> [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 81009a0..5286394 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -699,6 +699,7 @@ fs_inst::components_read(unsigned i) const
> case SHADER_OPCODE_LOD_LOGICAL:
> case SHADER_OPCODE_TG4_LOGICAL:
> case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
> + case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
> assert(src[8].file == IMM && src[9].file == IMM);
> /* Texture coordinates. */
> if (i == 0)
> @@ -875,6 +876,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
> case SHADER_OPCODE_TXL:
> case SHADER_OPCODE_TXS:
> case SHADER_OPCODE_LOD:
> + case SHADER_OPCODE_SAMPLEINFO:
> return 1;
> case FS_OPCODE_FB_WRITE:
> return 2;
> @@ -3709,6 +3711,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld,
> fs_inst *inst, opcode op,
> sources[i] = bld.vgrf(BRW_REGISTER_TYPE_F);
>
> if (op == SHADER_OPCODE_TG4 || op == SHADER_OPCODE_TG4_OFFSET ||
> + op == SHADER_OPCODE_SAMPLEINFO ||
> offset_value.file != BAD_FILE ||
> is_high_sampler(devinfo, sampler)) {
> /* For general texture offsets (no txf workaround), we need a header to
> @@ -4054,6 +4057,10 @@ fs_visitor::lower_logical_sends()
> lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4_OFFSET);
> break;
>
> + case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
> + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_SAMPLEINFO);
> + break;
> +
> case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
> lower_surface_logical_send(ibld, inst,
> SHADER_OPCODE_UNTYPED_SURFACE_READ,
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index c86ca04..90805e4 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -646,6 +646,9 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg
> dst, struct brw_reg src
> msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
> }
> break;
> + case SHADER_OPCODE_SAMPLEINFO:
> + msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
> + break;
> default:
> unreachable("not reached");
> }
> @@ -1920,6 +1923,7 @@ fs_generator::generate_code(const cfg_t *cfg, int
> dispatch_width)
> case SHADER_OPCODE_LOD:
> case SHADER_OPCODE_TG4:
> case SHADER_OPCODE_TG4_OFFSET:
> + case SHADER_OPCODE_SAMPLEINFO:
> generate_tex(inst, dst, src[0], src[1]);
> break;
> case FS_OPCODE_DDX_COARSE:
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index 430efb3..172e29f 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -1862,6 +1862,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld,
> nir_tex_instr *instr)
> switch (instr->op) {
> case nir_texop_lod: op = ir_lod; break;
> case nir_texop_query_levels: op = ir_query_levels; break;
> + case nir_texop_texture_samples: op = ir_texture_samples; break;
> case nir_texop_tex: op = ir_tex; break;
> case nir_texop_tg4: op = ir_tg4; break;
> case nir_texop_txb: op = ir_txb; break;
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 111db8c..0d511b4 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -300,6 +300,9 @@ fs_visitor::emit_texture(ir_texture_opcode op,
> opcode = (offset_value.file != BAD_FILE && offset_value.file != IMM ?
> SHADER_OPCODE_TG4_OFFSET_LOGICAL :
> SHADER_OPCODE_TG4_LOGICAL);
> break;
> + case ir_texture_samples:
> + opcode = SHADER_OPCODE_SAMPLEINFO_LOGICAL;
> + break;
> default:
> unreachable("Invalid texture opcode.");
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index 445764d..ee0b81d 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -621,6 +621,10 @@ brw_instruction_name(enum opcode op)
> return "tg4_offset";
> case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
> return "tg4_offset_logical";
> + case SHADER_OPCODE_SAMPLEINFO:
> + return "sampleinfo";
> + case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
> + return "sampleinfo_logical";
>
> case SHADER_OPCODE_SHADER_TIME_ADD:
> return "shader_time_add";
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index f18915a..0d8ff83 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -328,6 +328,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
> case SHADER_OPCODE_TXS:
> case SHADER_OPCODE_TG4:
> case SHADER_OPCODE_TG4_OFFSET:
> + case SHADER_OPCODE_SAMPLEINFO:
> return inst->header_size;
> default:
> unreachable("not reached");
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index 92050b9..1950333 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -286,6 +286,9 @@ vec4_generator::generate_tex(vec4_instruction *inst,
> msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
> }
> break;
> + case SHADER_OPCODE_SAMPLEINFO:
> + msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
> + break;
> default:
> unreachable("should not get here: invalid vec4 texture opcode");
> }
> @@ -1374,6 +1377,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
> case SHADER_OPCODE_TXS:
> case SHADER_OPCODE_TG4:
> case SHADER_OPCODE_TG4_OFFSET:
> + case SHADER_OPCODE_SAMPLEINFO:
> generate_tex(inst, dst, src[0], src[1]);
> break;
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 59e440a..38f0477 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -1353,6 +1353,7 @@ ir_texture_opcode_for_nir_texop(nir_texop texop)
> switch (texop) {
> case nir_texop_lod: op = ir_lod; break;
> case nir_texop_query_levels: op = ir_query_levels; break;
> + case nir_texop_texture_samples: op = ir_texture_samples; break;
> case nir_texop_tex: op = ir_tex; break;
> case nir_texop_tg4: op = ir_tg4; break;
> case nir_texop_txb: op = ir_txb; break;
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index ca86e8b..b2c30f5 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -2566,6 +2566,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
> case ir_tg4: opcode = offset_value.file != BAD_FILE
> ? SHADER_OPCODE_TG4_OFFSET : SHADER_OPCODE_TG4;
> break;
> case ir_query_levels: opcode = SHADER_OPCODE_TXS; break;
> + case ir_texture_samples: opcode = SHADER_OPCODE_SAMPLEINFO; break;
> case ir_txb:
> unreachable("TXB is not valid for vertex shaders.");
> case ir_lod:
> @@ -2585,13 +2586,15 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
> * - Texel offsets
> * - Gather channel selection
> * - Sampler indices too large to fit in a 4-bit value.
> + * - Sampleinfo message -- not really necessary but makes code simplerIt actually is necessary - the docs for the SEND instruction indicate that the minimum message length is 1. Since sampleinfo takes no data, and mlen = 0 is illegal, this implies that a header is required. I'd change this to: * - Sampleinfo message - takes no parameters, but mlen = 0 is illegal With that fixed, the series is: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Thanks for implementing this, Ilia!
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