In order to reduce later churn, move a few parameters from the general
brw_context into the intel_batchbuffer.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 20 ++++++++++++++++++
src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_compute.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.c | 9 +++------
src/mesa/drivers/dri/i965/brw_context.h | 19 ------------------
src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 29 +++++++++++++++------------
src/mesa/drivers/dri/i965/intel_screen.c | 4 ++--
8 files changed, 44 insertions(+), 43 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h
b/src/mesa/drivers/dri/i965/brw_batch.h
index 9e2d7fa..e3a83ea 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -69,6 +69,26 @@ typedef struct brw_batch {
dri_bufmgr *bufmgr;
+ /** Framerate throttling: @{ */
+ brw_bo *throttle_batch[2];
+
+ /* Limit the number of outstanding SwapBuffers by waiting for an earlier
+ * frame of rendering to complete. This gives a very precise cap to the
+ * latency between input and output such that rendering never gets more
+ * than a frame behind the user. (With the caveat that we technically are
+ * not using the SwapBuffers itself as a barrier but the first batch
+ * submitted afterwards, which may be immediately prior to the next
+ * SwapBuffers.)
+ */
+ bool need_swap_throttle;
+
+ /** General throttling, not caught by throttling between SwapBuffers */
+ bool need_flush_throttle;
+ /** @} */
+
+ bool always_flush : 1;
+ bool disable_throttling : 1;
+
/**
* Set of brw_bo* that have been rendered to within this batchbuffer
* and would need flushing before being used from another cache domain that
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 3804f24..55ccc4f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -269,7 +269,7 @@ retry:
}
}
- if (unlikely(brw->always_flush_batch))
+ if (unlikely(brw->batch.always_flush))
intel_batchbuffer_flush(brw);
/* We've smashed all state compared to what the normal 3D pipeline
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_compute.c
index 3342f39..c7a184e 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -144,7 +144,7 @@ brw_dispatch_compute(struct gl_context *ctx, const GLuint
*num_groups)
*/
brw_compute_state_finished(brw);
- if (brw->always_flush_batch)
+ if (brw->batch.always_flush)
intel_batchbuffer_flush(brw);
brw_state_cache_check_size(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 971d86d..12313ec 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -234,7 +234,7 @@ intel_glFlush(struct gl_context *ctx)
intel_flush_front(ctx);
- brw->need_flush_throttle = true;
+ brw->batch.need_flush_throttle = true;
}
static void
@@ -641,7 +641,7 @@ brw_process_driconf_options(struct brw_context *brw)
if (driQueryOptionb(options, "always_flush_batch")) {
fprintf(stderr, "flushing batchbuffer before/after each draw call\n");
- brw->always_flush_batch = true;
+ brw->batch.always_flush = true;
}
if (driQueryOptionb(options, "always_flush_cache")) {
@@ -651,7 +651,7 @@ brw_process_driconf_options(struct brw_context *brw)
if (driQueryOptionb(options, "disable_throttling")) {
fprintf(stderr, "disabling flush throttling\n");
- brw->disable_throttling = true;
+ brw->batch.disable_throttling = true;
}
brw->precompile = driQueryOptionb(&brw->optionCache, "shader_precompile");
@@ -950,9 +950,6 @@ intelDestroyContext(__DRIcontext * driContextPriv)
brw_fini_pipe_control(brw);
intel_batchbuffer_free(brw);
- brw_bo_put(brw->throttle_batch[1]);
- brw_bo_put(brw->throttle_batch[0]);
-
driDestroyOptionCache(&brw->optionCache);
/* free the Mesa context */
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 6301da4..a4169f4 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1030,23 +1030,6 @@ struct brw_context
*/
bool front_buffer_dirty;
- /** Framerate throttling: @{ */
- brw_bo *throttle_batch[2];
-
- /* Limit the number of outstanding SwapBuffers by waiting for an earlier
- * frame of rendering to complete. This gives a very precise cap to the
- * latency between input and output such that rendering never gets more
- * than a frame behind the user. (With the caveat that we technically are
- * not using the SwapBuffers itself as a barrier but the first batch
- * submitted afterwards, which may be immediately prior to the next
- * SwapBuffers.)
- */
- bool need_swap_throttle;
-
- /** General throttling, not caught by throttling between SwapBuffers */
- bool need_flush_throttle;
- /** @} */
-
GLuint stats_wm;
driOptionCache optionCache;
@@ -1106,9 +1089,7 @@ struct brw_context
* @{
*/
bool no_rast : 1;
- bool always_flush_batch : 1;
bool always_flush_cache : 1;
- bool disable_throttling : 1;
bool precompile : 1;
GLuint NewGLState;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 611abea..53364a1 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -537,7 +537,7 @@ retry:
brw_render_state_finished(brw);
}
- if (brw->always_flush_batch)
+ if (brw->batch.always_flush)
intel_batchbuffer_flush(brw);
brw_state_cache_check_size(brw);
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 712eee0..e57463d 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -103,6 +103,9 @@ intel_batchbuffer_free(struct brw_context *brw)
free(brw->batch.cpu_map);
brw_bo_put(brw->batch.last_bo);
brw_bo_put(brw->batch.bo);
+
+ brw_bo_put(brw->batch.throttle_batch[1]);
+ brw_bo_put(brw->batch.throttle_batch[0]);
}
static void
@@ -257,23 +260,23 @@ throttle(struct brw_context *brw)
* the swap, and getting our hands on that doesn't seem worth it,
* so we just use the first batch we emitted after the last swap.
*/
- if (brw->need_swap_throttle && brw->throttle_batch[0]) {
- if (brw->throttle_batch[1]) {
- if (!brw->disable_throttling)
- drm_intel_bo_wait_rendering(brw->throttle_batch[1]);
- brw_bo_put(brw->throttle_batch[1]);
+ if (brw->batch.need_swap_throttle && brw->batch.throttle_batch[0]) {
+ if (brw->batch.throttle_batch[1]) {
+ if (!brw->batch.disable_throttling)
+ drm_intel_bo_wait_rendering(brw->batch.throttle_batch[1]);
+ brw_bo_put(brw->batch.throttle_batch[1]);
}
- brw->throttle_batch[1] = brw->throttle_batch[0];
- brw->throttle_batch[0] = NULL;
- brw->need_swap_throttle = false;
+ brw->batch.throttle_batch[1] = brw->batch.throttle_batch[0];
+ brw->batch.throttle_batch[0] = NULL;
+ brw->batch.need_swap_throttle = false;
/* Throttling here is more precise than the throttle ioctl, so skip it */
- brw->need_flush_throttle = false;
+ brw->batch.need_flush_throttle = false;
}
- if (brw->need_flush_throttle) {
+ if (brw->batch.need_flush_throttle) {
__DRIscreen *psp = brw->intelScreen->driScrnPriv;
drmCommandNone(psp->fd, DRM_I915_GEM_THROTTLE);
- brw->need_flush_throttle = false;
+ brw->batch.need_flush_throttle = false;
}
}
@@ -350,8 +353,8 @@ _intel_batchbuffer_flush(struct brw_context *brw,
if (USED_BATCH(brw->batch) == 0)
return 0;
- if (brw->throttle_batch[0] == NULL)
- brw->throttle_batch[0] = brw_bo_get(brw->batch.bo);
+ if (brw->batch.throttle_batch[0] == NULL)
+ brw->batch.throttle_batch[0] = brw_bo_get(brw->batch.bo);
if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
int bytes_for_commands = 4 * USED_BATCH(brw->batch);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index c84f495..5b3ad24 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -177,9 +177,9 @@ intel_dri2_flush_with_flags(__DRIcontext *cPriv,
intel_resolve_for_dri2_flush(brw, dPriv);
if (reason == __DRI2_THROTTLE_SWAPBUFFER)
- brw->need_swap_throttle = true;
+ brw->batch.need_swap_throttle = true;
if (reason == __DRI2_THROTTLE_FLUSHFRONT)
- brw->need_flush_throttle = true;
+ brw->batch.need_flush_throttle = true;
intel_batchbuffer_flush(brw);
--
2.5.0
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