We have a few instances where we set a register to an immediate value
(MI_LOAD_REGISTER_IMM), so let's replace them with a simple routine.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_draw.c | 6 +-----
src/mesa/drivers/dri/i965/brw_performance_monitor.c | 17 ++++++-----------
src/mesa/drivers/dri/i965/brw_pipelined_register.c | 12 ++++++++++++
src/mesa/drivers/dri/i965/brw_pipelined_register.h | 4 ++++
src/mesa/drivers/dri/i965/brw_state_upload.c | 11 +++++------
src/mesa/drivers/dri/i965/gen7_sol_state.c | 6 +-----
src/mesa/drivers/dri/i965/gen8_depth_state.c | 9 ++++-----
7 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index c819bb7..611abea 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -248,11 +248,7 @@ brw_emit_prim(struct brw_context *brw,
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 12);
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
- OUT_BATCH(0);
- ADVANCE_BATCH();
+ brw_load_register_imm(brw, GEN7_3DPRIM_BASE_VERTEX, 0);
}
} else {
indirect_flag = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
index 1afc968..b92b1d7 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
@@ -54,6 +54,7 @@
#include "brw_context.h"
#include "brw_defines.h"
+#include "brw_pipelined_register.h"
#include "intel_reg.h"
@@ -659,12 +660,10 @@ start_oa_counters(struct brw_context *brw)
unreachable("Tried to enable OA counters on an unsupported generation.");
}
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(OACONTROL);
- OUT_BATCH(counter_format << OACONTROL_COUNTER_SELECT_SHIFT |
- OACONTROL_ENABLE_COUNTERS);
- ADVANCE_BATCH();
+ brw_load_register_imm(brw,
+ OACONTROL,
+ counter_format << OACONTROL_COUNTER_SELECT_SHIFT |
+ OACONTROL_ENABLE_COUNTERS);
}
/**
@@ -677,11 +676,7 @@ stop_oa_counters(struct brw_context *brw)
if (brw->gen == 5)
return;
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(OACONTROL);
- OUT_BATCH(0);
- ADVANCE_BATCH();
+ brw_load_register_imm(brw, OACONTROL, 0);
}
/**
diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.c
b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
index 9424e4a..07335d9 100644
--- a/src/mesa/drivers/dri/i965/brw_pipelined_register.c
+++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
@@ -77,3 +77,15 @@ brw_load_register_mem64(struct brw_context *brw,
{
load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset,
2);
}
+
+void
+brw_load_register_imm(struct brw_context *brw,
+ uint32_t reg,
+ uint32_t value)
+{
+ BEGIN_BATCH(3);
+ OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+ OUT_BATCH(reg);
+ OUT_BATCH(value);
+ ADVANCE_BATCH();
+}
diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.h
b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
index c3dd02f..d3fea14 100644
--- a/src/mesa/drivers/dri/i965/brw_pipelined_register.h
+++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
@@ -28,6 +28,10 @@
extern "C" {
#endif
+void brw_load_register_imm(struct brw_context *brw,
+ uint32_t reg,
+ uint32_t value);
+
void brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
brw_bo *bo,
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 03e9c3b..c2af48c 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -41,6 +41,7 @@
#include "brw_gs.h"
#include "brw_wm.h"
#include "brw_cs.h"
+#include "brw_pipelined_register.h"
#include "main/framebuffer.h"
static const struct brw_tracked_state *gen4_atoms[] =
@@ -359,12 +360,10 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
/* Recommended optimization for Victim Cache eviction in pixel backend. */
if (brw->gen >= 9) {
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(GEN7_CACHE_MODE_1);
- OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) |
- GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
- ADVANCE_BATCH();
+ brw_load_register_imm(brw,
+ GEN7_CACHE_MODE_1,
+ (GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) |
+ GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
}
if (brw->gen >= 8) {
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index c863dfc..8eca604 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -466,11 +466,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx,
GLenum mode,
/* Reset the SOL buffer offset registers. */
if (brw->gen == 7 && brw->has_pipelined_so) {
for (int i = 0; i < 4; i++) {
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
- OUT_BATCH(0);
- ADVANCE_BATCH();
+ brw_load_register_imm(brw, GEN7_SO_WRITE_OFFSET(i), 0);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 05a003f..3a6a763 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -26,6 +26,7 @@
#include "intel_resolve_map.h"
#include "intel_reg.h"
#include "brw_context.h"
+#include "brw_pipelined_register.h"
#include "brw_state.h"
#include "brw_defines.h"
#include "brw_wm.h"
@@ -344,11 +345,9 @@ write_pma_stall_bits(struct brw_context *brw, uint32_t
pma_stall_bits)
render_cache_flush);
/* CACHE_MODE_1 is a non-privileged register. */
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(GEN7_CACHE_MODE_1);
- OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
- ADVANCE_BATCH();
+ brw_load_register_imm(brw,
+ GEN7_CACHE_MODE_1,
+ GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
/* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
* Flush bits is often necessary. We do it regardless because it's easier.
--
2.5.0
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