As of this commit, nothing actually needs the brw_context.
---
src/mesa/drivers/dri/i965/brw_cs.cpp | 6 ++++--
src/mesa/drivers/dri/i965/brw_fs.cpp | 12 ++++++------
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 1 -
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_shader.cpp | 9 +++++----
src/mesa/drivers/dri/i965/brw_shader.h | 7 ++++---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 6 ++++--
src/mesa/drivers/dri/i965/brw_vec4.h | 2 +-
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 14 ++++++++------
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h | 2 +-
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 1 -
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_vs.h | 2 +-
src/mesa/drivers/dri/i965/gen6_gs_visitor.h | 4 ++--
16 files changed, 43 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cs.cpp
b/src/mesa/drivers/dri/i965/brw_cs.cpp
index fa8b5c8..4c5082c 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_cs.cpp
@@ -94,7 +94,8 @@ brw_cs_emit(struct brw_context *brw,
/* Now the main event: Visit the shader IR and generate our CS IR for it.
*/
- fs_visitor v8(brw, mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base,
prog,
+ fs_visitor v8(brw->intelScreen->compiler, brw,
+ mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base, prog,
&cp->Base, 8, st_index);
if (!v8.run_cs()) {
fail_msg = v8.fail_msg;
@@ -103,7 +104,8 @@ brw_cs_emit(struct brw_context *brw,
prog_data->simd_size = 8;
}
- fs_visitor v16(brw, mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base,
prog,
+ fs_visitor v16(brw->intelScreen->compiler, brw,
+ mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base, prog,
&cp->Base, 16, st_index);
if (likely(!(INTEL_DEBUG & DEBUG_NO16)) &&
!fail_msg && !v8.simd16_unsupported &&
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 23f60c2..f7f05af 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -677,8 +677,7 @@ fs_visitor::no16(const char *msg)
} else {
simd16_unsupported = true;
- struct brw_compiler *compiler = brw->intelScreen->compiler;
- compiler->shader_perf_log(brw,
+ compiler->shader_perf_log(log_data,
"SIMD16 shader failed to compile: %s", msg);
}
}
@@ -3757,8 +3756,7 @@ fs_visitor::allocate_registers()
fail("Failure to register allocate. Reduce number of "
"live scalar values to avoid this.");
} else {
- struct brw_compiler *compiler = brw->intelScreen->compiler;
- compiler->shader_perf_log(brw,
+ compiler->shader_perf_log(log_data,
"%s shader triggered register spilling. "
"Try reducing the number of live scalar "
"values to improve performance.\n",
@@ -3994,7 +3992,8 @@ brw_wm_fs_emit(struct brw_context *brw,
/* Now the main event: Visit the shader IR and generate our FS IR for it.
*/
- fs_visitor v(brw, mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
+ fs_visitor v(brw->intelScreen->compiler, brw,
+ mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
prog, &fp->Base, 8, st_index8);
if (!v.run_fs(false /* do_rep_send */)) {
if (prog) {
@@ -4009,7 +4008,8 @@ brw_wm_fs_emit(struct brw_context *brw,
}
cfg_t *simd16_cfg = NULL;
- fs_visitor v2(brw, mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
+ fs_visitor v2(brw->intelScreen->compiler, brw,
+ mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
prog, &fp->Base, 16, st_index16);
if (likely(!(INTEL_DEBUG & DEBUG_NO16) || brw->use_rep_send)) {
if (!v.simd16_unsupported) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index e0a8984..243baf6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -70,7 +70,7 @@ namespace brw {
class fs_visitor : public backend_shader
{
public:
- fs_visitor(struct brw_context *brw,
+ fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
gl_shader_stage stage,
const void *key,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index cd78816..364fc4a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -535,7 +535,6 @@ setup_mrf_hack_interference(fs_visitor *v, struct ra_graph
*g,
bool
fs_visitor::assign_regs(bool allow_spilling)
{
- struct brw_compiler *compiler = brw->intelScreen->compiler;
/* Most of this allocation was written for a reg_width of 1
* (dispatch_width == 8). In extending to SIMD16, the code was
* left in place and it was converted to have the hardware
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 395394c..72d6a28 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1975,7 +1975,7 @@ fs_visitor::emit_barrier()
bld.exec_all().emit(SHADER_OPCODE_BARRIER, reg_undef, payload);
}
-fs_visitor::fs_visitor(struct brw_context *brw,
+fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
gl_shader_stage stage,
const void *key,
@@ -1984,7 +1984,7 @@ fs_visitor::fs_visitor(struct brw_context *brw,
struct gl_program *prog,
unsigned dispatch_width,
int shader_time_index)
- : backend_shader(brw, shader_prog, prog, prog_data, stage),
+ : backend_shader(compiler, log_data, shader_prog, prog, prog_data, stage),
key(key), prog_data(prog_data),
dispatch_width(dispatch_width),
shader_time_index(shader_time_index),
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 683946b..0b38252 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -845,14 +845,15 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg
*reg)
return false;
}
-backend_shader::backend_shader(struct brw_context *brw,
+backend_shader::backend_shader(const struct brw_compiler *compiler,
+ void *log_data,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
gl_shader_stage stage)
- : brw(brw),
- devinfo(brw->intelScreen->devinfo),
- ctx(&brw->ctx),
+ : compiler(compiler),
+ log_data(log_data),
+ devinfo(compiler->devinfo),
shader(shader_prog ?
(struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
shader_prog(shader_prog),
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index b5408a9..8d31816 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -220,7 +220,7 @@ enum instruction_scheduler_mode {
class backend_shader {
protected:
- backend_shader(struct brw_context *brw,
+ backend_shader(const struct brw_compiler *compiler, void *log_data,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
@@ -228,9 +228,10 @@ protected:
public:
- struct brw_context * const brw;
+ const struct brw_compiler *compiler;
+ void *log_data; /* Passed to compiler->*_log functions */
+
const struct brw_device_info * const devinfo;
- struct gl_context * const ctx;
struct brw_shader * const shader;
struct gl_shader_program * const shader_prog;
struct gl_program * const prog;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index f51aa1a..a5c686c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1899,7 +1899,8 @@ brw_vs_emit(struct brw_context *brw,
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
- fs_visitor v(brw, mem_ctx, MESA_SHADER_VERTEX, &c->key,
+ fs_visitor v(brw->intelScreen->compiler, brw,
+ mem_ctx, MESA_SHADER_VERTEX, &c->key,
&prog_data->base.base, prog, &c->vp->program.Base,
8, st_index);
if (!v.run_vs(brw_select_clip_planes(&brw->ctx))) {
@@ -1939,7 +1940,8 @@ brw_vs_emit(struct brw_context *brw,
if (!assembly) {
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
- vec4_vs_visitor v(brw, c, prog_data, prog, mem_ctx, st_index,
+ vec4_vs_visitor v(brw->intelScreen->compiler,
+ c, prog_data, prog, mem_ctx, st_index,
!_mesa_is_gles3(&brw->ctx));
if (!v.run(brw_select_clip_planes(&brw->ctx))) {
if (prog) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 193b381..2ac1693 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -76,7 +76,7 @@ class vec4_live_variables;
class vec4_visitor : public backend_shader, public ir_visitor
{
public:
- vec4_visitor(struct brw_context *brw,
+ vec4_visitor(const struct brw_compiler *compiler,
struct brw_vec4_compile *c,
struct gl_program *prog,
const struct brw_vue_prog_key *key,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index d876762..69bcf5a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -34,13 +34,13 @@ const unsigned MAX_GS_INPUT_VERTICES = 6;
namespace brw {
-vec4_gs_visitor::vec4_gs_visitor(struct brw_context *brw,
+vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler *compiler,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
void *mem_ctx,
bool no_spills,
int shader_time_index)
- : vec4_visitor(brw, &c->base, &c->gp->program.Base, &c->key.base,
+ : vec4_visitor(compiler, &c->base, &c->gp->program.Base, &c->key.base,
&c->prog_data.base, prog, MESA_SHADER_GEOMETRY, mem_ctx,
no_spills, shader_time_index),
c(c)
@@ -662,8 +662,8 @@ brw_gs_emit(struct brw_context *brw,
likely(!(INTEL_DEBUG & DEBUG_NO_DUAL_OBJECT_GS))) {
c->prog_data.base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
- vec4_gs_visitor v(brw, c, prog, mem_ctx, true /* no_spills */,
- st_index);
+ vec4_gs_visitor v(brw->intelScreen->compiler,
+ c, prog, mem_ctx, true /* no_spills */, st_index);
if (v.run(NULL /* clip planes */)) {
return generate_assembly(brw, prog, &c->gp->program.Base,
&c->prog_data.base, mem_ctx, v.cfg,
@@ -704,10 +704,12 @@ brw_gs_emit(struct brw_context *brw,
const unsigned *ret = NULL;
if (brw->gen >= 7)
- gs = new vec4_gs_visitor(brw, c, prog, mem_ctx, false /* no_spills */,
+ gs = new vec4_gs_visitor(brw->intelScreen->compiler,
+ c, prog, mem_ctx, false /* no_spills */,
st_index);
else
- gs = new gen6_gs_visitor(brw, c, prog, mem_ctx, false /* no_spills */,
+ gs = new gen6_gs_visitor(brw->intelScreen->compiler,
+ c, prog, mem_ctx, false /* no_spills */,
st_index);
if (!gs->run(NULL /* clip planes */)) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
index f42311d..e693c56 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
@@ -68,7 +68,7 @@ namespace brw {
class vec4_gs_visitor : public vec4_visitor
{
public:
- vec4_gs_visitor(struct brw_context *brw,
+ vec4_gs_visitor(const struct brw_compiler *compiler,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
void *mem_ctx,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 5368a75..555c42e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -191,7 +191,6 @@ vec4_visitor::setup_payload_interference(struct ra_graph *g,
bool
vec4_visitor::reg_allocate()
{
- struct brw_compiler *compiler = brw->intelScreen->compiler;
unsigned int hw_reg_mapping[alloc.count];
int payload_reg_count = this->first_non_payload_grf;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index dd50dfa..553d8a8 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -3677,7 +3677,7 @@ vec4_visitor::resolve_bool_comparison(ir_rvalue *rvalue,
src_reg *reg)
*reg = neg_result;
}
-vec4_visitor::vec4_visitor(struct brw_context *brw,
+vec4_visitor::vec4_visitor(const struct brw_compiler *compiler,
struct brw_vec4_compile *c,
struct gl_program *prog,
const struct brw_vue_prog_key *key,
@@ -3687,7 +3687,7 @@ vec4_visitor::vec4_visitor(struct brw_context *brw,
void *mem_ctx,
bool no_spills,
int shader_time_index)
- : backend_shader(brw, shader_prog, prog, &prog_data->base, stage),
+ : backend_shader(compiler, NULL, shader_prog, prog, &prog_data->base,
stage),
c(c),
key(key),
prog_data(prog_data),
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
index 26e3057..f93062b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
@@ -211,14 +211,14 @@ vec4_vs_visitor::emit_thread_end()
}
-vec4_vs_visitor::vec4_vs_visitor(struct brw_context *brw,
+vec4_vs_visitor::vec4_vs_visitor(const struct brw_compiler *compiler,
struct brw_vs_compile *vs_compile,
struct brw_vs_prog_data *vs_prog_data,
struct gl_shader_program *prog,
void *mem_ctx,
int shader_time_index,
bool use_legacy_snorm_formula)
- : vec4_visitor(brw, &vs_compile->base, &vs_compile->vp->program.Base,
+ : vec4_visitor(compiler, &vs_compile->base, &vs_compile->vp->program.Base,
&vs_compile->key.base, &vs_prog_data->base, prog,
MESA_SHADER_VERTEX,
mem_ctx, false /* no_spills */,
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h
b/src/mesa/drivers/dri/i965/brw_vs.h
index 0511ab5..61f9b00 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -90,7 +90,7 @@ namespace brw {
class vec4_vs_visitor : public vec4_visitor
{
public:
- vec4_vs_visitor(struct brw_context *brw,
+ vec4_vs_visitor(const struct brw_compiler *compiler,
struct brw_vs_compile *vs_compile,
struct brw_vs_prog_data *vs_prog_data,
struct gl_shader_program *prog,
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_visitor.h
b/src/mesa/drivers/dri/i965/gen6_gs_visitor.h
index 863fbd0..27254eb 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_visitor.h
+++ b/src/mesa/drivers/dri/i965/gen6_gs_visitor.h
@@ -35,13 +35,13 @@ namespace brw {
class gen6_gs_visitor : public vec4_gs_visitor
{
public:
- gen6_gs_visitor(struct brw_context *brw,
+ gen6_gs_visitor(const struct brw_compiler *comp,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
void *mem_ctx,
bool no_spills,
int shader_time_index) :
- vec4_gs_visitor(brw, c, prog, mem_ctx, no_spills, shader_time_index) {}
+ vec4_gs_visitor(comp, c, prog, mem_ctx, no_spills, shader_time_index) {}
protected:
virtual void assign_binding_table_offsets();
--
2.4.3
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