On Wed, May 20, 2015 at 09:32:09AM +0300, Abdiel Janulgue wrote:
> Unlike normal software binding tables where the driver has to manually
> generate and fill a binding table array which are then uploaded to the
> hardware, the resource streamer instead presents the driver with an option
> to fill out slots for individual binding table indices. The hardware
> accumlates the state for these combined edits which it then automatically
> flushes to a binding table pool when the binding table pointer state
> command is invoked.
>
> Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_binding_tables.c | 50
> ++++++++++++++++++++++++++
> src/mesa/drivers/dri/i965/brw_state.h | 9 +++++
> 2 files changed, 59 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c
> b/src/mesa/drivers/dri/i965/brw_binding_tables.c
> index d8cb96d..e0ee700 100644
> --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
> +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
> @@ -61,6 +61,12 @@
> */
> #define HW_BT_START_OFFSET 2 * 256;
>
> +static const GLuint stage_to_bt_edit[MESA_SHADER_FRAGMENT + 1] = {
> + _3DSTATE_BINDING_TABLE_EDIT_VS,
> + _3DSTATE_BINDING_TABLE_EDIT_GS,
> + _3DSTATE_BINDING_TABLE_EDIT_PS,
> +};
> +
> /**
> * Upload a shader stage's binding table as indirect state.
> *
> @@ -191,6 +197,50 @@ const struct brw_tracked_state brw_gs_binding_table = {
> * Hardware-generated binding tables for the resource streamer
> */
> void
> +gen7_update_binding_table(struct brw_context *brw,
> + gl_shader_stage stage,
> + uint32_t index,
> + uint32_t surf_offset)
> +{
> + assert(stage <= MESA_SHADER_FRAGMENT);
> +
> + /* The surface state offset is a 16-bit value aligned to 32 bytes but
> + * Surface State Pointer in dw2 is [15:0]. Right shift surf_offset
> + * by 5 bits so it won't disturb bit 16 (which is used as the binding
> + * table index entry), otherwise it would hang the GPU.
> + */
> + uint32_t dw2 = SET_FIELD(index, BRW_BINDING_TABLE_INDEX) | (surf_offset
> >> 5);
How about creating a macro for the shift along with the documentation above -
I see the same shift below in gen7_update_binding_table_from_array() without
the explanation.
> +
> + BEGIN_BATCH(3);
> + OUT_BATCH(stage_to_bt_edit[stage] << 16 | (3 - 2));
> + OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL);
> + OUT_BATCH(dw2);
> + ADVANCE_BATCH();
> +}
> +
> +/**
> + * Hardware-generated binding tables for the resource streamer
> + */
> +void
> +gen7_update_binding_table_from_array(struct brw_context *brw,
> + gl_shader_stage stage,
> + const uint32_t* binding_table,
> + int size)
> +{
> + uint32_t dw2 = 0;
> + assert(stage <= MESA_SHADER_FRAGMENT);
> +
> + BEGIN_BATCH(size + 2);
> + OUT_BATCH(stage_to_bt_edit[stage] << 16 | size);
> + OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL);
> + for (int i = 0; i < size; i++) {
> + dw2 = SET_FIELD(i, BRW_BINDING_TABLE_INDEX) | (binding_table[i] >> 5);
> + OUT_BATCH(dw2);
> + }
> + ADVANCE_BATCH();
> +}
> +
> +void
> gen7_disable_hw_binding_tables(struct brw_context *brw)
> {
> BEGIN_BATCH(3);
> diff --git a/src/mesa/drivers/dri/i965/brw_state.h
> b/src/mesa/drivers/dri/i965/brw_state.h
> index 52dea58..b296e54 100644
> --- a/src/mesa/drivers/dri/i965/brw_state.h
> +++ b/src/mesa/drivers/dri/i965/brw_state.h
> @@ -375,6 +375,15 @@ gen7_upload_constant_state(struct brw_context *brw,
>
> /* gen7_misc_state.c */
> void gen7_rs_control(struct brw_context *brw, int enable);
> +
> +void gen7_update_binding_table(struct brw_context *brw,
> + gl_shader_stage stage,
> + uint32_t index,
> + uint32_t surf_offset);
> +void gen7_update_binding_table_from_array(struct brw_context *brw,
> + gl_shader_stage stage,
> + const uint32_t* binding_table,
> + int size);
> void gen7_enable_hw_binding_tables(struct brw_context *brw);
> void gen7_disable_hw_binding_tables(struct brw_context *brw);
> void gen7_reset_rs_pool_offsets(struct brw_context *brw);
> --
> 1.9.1
>
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