On Tue, May 19, 2015 at 5:48 PM, Nanley Chery <nanleych...@gmail.com> wrote: > From: Nanley Chery <nanley.g.ch...@intel.com> > > Intel surface formats default to LDR unless there is hardware > support for HDR and the texture is able to be processed in HDR mode. > > Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com> > --- > src/mesa/drivers/dri/i965/brw_defines.h | 36 +++++++++++++ > src/mesa/drivers/dri/i965/brw_surface_formats.c | 67 > ++++++++++++++++++++++++- > 2 files changed, 101 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h > b/src/mesa/drivers/dri/i965/brw_defines.h > index dedc381..6d5ec02 100644 > --- a/src/mesa/drivers/dri/i965/brw_defines.h > +++ b/src/mesa/drivers/dri/i965/brw_defines.h > @@ -266,6 +266,7 @@ > > /* Surface state DW0 */ > #define GEN8_SURFACE_IS_ARRAY (1 << 28) > +
Unnecessary whitespace change? > #define GEN8_SURFACE_VALIGN_4 (1 << 16) > #define GEN8_SURFACE_VALIGN_8 (2 << 16) > #define GEN8_SURFACE_VALIGN_16 (3 << 16) > @@ -504,6 +505,40 @@ > #define BRW_SURFACEFORMAT_R8G8B8_UINT 0x1C8 > #define BRW_SURFACEFORMAT_R8G8B8_SINT 0x1C9 > #define BRW_SURFACEFORMAT_RAW 0x1FF > + > +#define GEN9_SURFACE_ASTC_HDR_FORMAT_BIT 0x100 > +#define GEN9_SURFACE_ASTC_ENABLE 0x200 > + > +/* The following formats have GEN9_SURFACE_ASTC_ENABLE built in: */ > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_4x4_U8sRGB 0x200 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x4_U8sRGB 0x208 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x5_U8sRGB 0x209 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x5_U8sRGB 0x211 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x6_U8sRGB 0x212 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x5_U8sRGB 0x221 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x6_U8sRGB 0x222 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x8_U8sRGB 0x224 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x5_U8sRGB 0x231 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x6_U8sRGB 0x232 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x8_U8sRGB 0x234 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x10_U8sRGB 0x236 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x10_U8sRGB 0x23E > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x12_U8sRGB 0x23F > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_4x4_FLT16 0x240 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x4_FLT16 0x248 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x5_FLT16 0x249 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x5_FLT16 0x251 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x6_FLT16 0x252 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x5_FLT16 0x261 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x6_FLT16 0x262 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x8_FLT16 0x264 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x5_FLT16 0x271 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x6_FLT16 0x272 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x8_FLT16 0x274 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x10_FLT16 0x276 > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x10_FLT16 0x27E > +#define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x12_FLT16 0x27F > + > #define BRW_SURFACE_FORMAT_SHIFT 18 > #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18) > > @@ -519,6 +554,7 @@ > #define BRW_SURFACE_BUFFER 4 > #define BRW_SURFACE_NULL 7 > > + Extra newline > #define GEN7_SURFACE_IS_ARRAY (1 << 28) > #define GEN7_SURFACE_VALIGN_2 (0 << 16) > #define GEN7_SURFACE_VALIGN_4 (1 << 16) _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
