---
src/mesa/drivers/dri/i965/brw_ir_vec4.h | 6 +-----
src/mesa/drivers/dri/i965/brw_reg.h | 6 ++----
src/mesa/drivers/dri/i965/brw_vec4.cpp | 8 ++------
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 6 +++---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 15 +++------------
5 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 73ffa00..4e6203e 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -83,11 +83,7 @@ static inline src_reg
swizzle(src_reg reg, unsigned swizzle)
{
assert(reg.file != HW_REG);
- reg.swizzle = BRW_SWIZZLE4(
- BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)),
- BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)),
- BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)),
- BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3)));
+ reg.swizzle = brw_compose_swizzle(swizzle, reg.swizzle);
return reg;
}
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index 9eb076f..abb008c 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -895,10 +895,8 @@ brw_swizzle(struct brw_reg reg, unsigned x, unsigned y,
unsigned z, unsigned w)
{
assert(reg.file != BRW_IMMEDIATE_VALUE);
- reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
- BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
- BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
- BRW_GET_SWZ(reg.dw1.bits.swizzle, w));
+ reg.dw1.bits.swizzle = brw_compose_swizzle(BRW_SWIZZLE4(x, y, z, w),
+ reg.dw1.bits.swizzle);
return reg;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index a6842fc..8e4df8c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -572,12 +572,8 @@ vec4_visitor::pack_uniform_registers()
continue;
inst->src[i].reg = new_loc[src];
-
- int sx = BRW_GET_SWZ(inst->src[i].swizzle, 0) + new_chan[src];
- int sy = BRW_GET_SWZ(inst->src[i].swizzle, 1) + new_chan[src];
- int sz = BRW_GET_SWZ(inst->src[i].swizzle, 2) + new_chan[src];
- int sw = BRW_GET_SWZ(inst->src[i].swizzle, 3) + new_chan[src];
- inst->src[i].swizzle = BRW_SWIZZLE4(sx, sy, sz, sw);
+ inst->src[i].swizzle += BRW_SWIZZLE4(new_chan[src], new_chan[src],
+ new_chan[src], new_chan[src]);
}
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index 2df64e2..9b7ebf9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -275,10 +275,10 @@ try_copy_propagate(struct brw_context *brw,
vec4_instruction *inst,
*/
int s[4];
for (int i = 0; i < 4; i++) {
- s[i] = BRW_GET_SWZ(entry->value[i]->swizzle,
- BRW_GET_SWZ(inst->src[arg].swizzle, i));
+ s[i] = BRW_GET_SWZ(entry->value[i]->swizzle, i);
}
- value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
+ value.swizzle = brw_compose_swizzle(inst->src[arg].swizzle,
+ BRW_SWIZZLE4(s[0], s[1], s[2], s[3]));
if (value.file != UNIFORM &&
value.file != GRF &&
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 8ae1abc..d298540 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -3347,18 +3347,9 @@ vec4_visitor::emit_scratch_write(bblock_t *block,
vec4_instruction *inst,
* weren't initialized, it will confuse live interval analysis, which will
* make spilling fail to make progress.
*/
- src_reg temp = src_reg(this, glsl_type::vec4_type);
- temp.type = inst->dst.type;
- int first_writemask_chan = ffs(inst->dst.writemask) - 1;
- int swizzles[4];
- for (int i = 0; i < 4; i++)
- if (inst->dst.writemask & (1 << i))
- swizzles[i] = i;
- else
- swizzles[i] = first_writemask_chan;
- temp.swizzle = BRW_SWIZZLE4(swizzles[0], swizzles[1],
- swizzles[2], swizzles[3]);
-
+ const src_reg temp = swizzle(retype(src_reg(this, glsl_type::vec4_type),
+ inst->dst.type),
+ brw_swizzle_for_mask(inst->dst.writemask));
dst_reg dst = dst_reg(brw_writemask(brw_vec8_grf(0, 0),
inst->dst.writemask));
vec4_instruction *write = SCRATCH_WRITE(dst, temp, index);
--
2.1.3
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