Steppings C0 and D0 of Skylake fail when using SIMD16 with 3-source
instructions (such as MAD). This patch just makes it disable SIMD16 in
those cases.
This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit
tests.
v2: Also apply on stepping D0
---
Damien Lespiau pointed out that the workaround also needs to be
applied on stepping D0.
src/mesa/drivers/dri/i965/brw_fs.cpp | 22 ++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 533feb4..b61208b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3729,6 +3729,27 @@ fs_visitor::fixup_3src_null_dest()
}
}
+/**
+ * 3-source instructions don't work on Skylake steppings C0 and D0. If the
+ * revision isn't known then it will take the safe option and disable it in
+ * case it's one of those. Implements WaDisableSIMD16On3SrcInstr.
+ */
+void
+fs_visitor::disable_simd16_with_3src()
+{
+ if (brw->gen != 9 ||
+ (brw->revision != 2 && brw->revision != 3 && brw->revision != -1))
+ return;
+
+ foreach_block_and_inst_safe (block, fs_inst, inst, cfg) {
+ if (inst->is_3src()) {
+ no16("SIMD16 doesn't work with 3-source instructions on "
+ "Gen9 steppings C0 and D0\n");
+ return;
+ }
+ }
+}
+
void
fs_visitor::allocate_registers()
{
@@ -3910,6 +3931,7 @@ fs_visitor::run_fs()
assign_urb_setup();
fixup_3src_null_dest();
+ disable_simd16_with_3src();
allocate_registers();
if (failed)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 70098d8..7091b9f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -196,6 +196,7 @@ public:
void setup_payload_gen6();
void setup_vs_payload();
void fixup_3src_null_dest();
+ void disable_simd16_with_3src();
void assign_curb_setup();
void calculate_urb_setup();
void assign_urb_setup();
--
1.9.3
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