Ilia Mirkin <imir...@alum.mit.edu> writes: > On Wed, Mar 4, 2015 at 9:33 AM, Neil Roberts <n...@linux.intel.com> wrote: >> Stepping C0 of Skylake fails when using SIMD16 with 3-source >> instructions (such as MAD). This patch just makes it disable SIMD16 in >> that case. >> >> This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit >> tests. > > Just curious -- is this faster than lowering MAD into MUL + ADD but > staying in SIMD16? (Should be fairly easy to implement as a post-RA > fixup I'd think, although not totally familiar with how the i965 > compiler works.)
I haven't tested it but I think you're right that it would probably be faster to lower the instruction. However that sounds like more work and it's only relevant for a limited set of hardware so it doesn't seem worth doing. I think there are also other 3-source instructions and it might be more difficult to lower those (although I'm not sure). Regards, - Neil _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
