And remove the mocs argument of the emit_buffer_surface_state vtbl hook. Its
semantics vary greatly from one generation to another, so it kind of
encourages the caller to pass 0 which is the only valid setting across
generations. After this commit the hardware-specific code decides what the
best cacheability settings are for buffer surfaces, just like we do for
textures.
This together with some additional changes coming is expected to improve
performance of pull constants, buffer textures, atomic counters and image
objects on Gen7 and up.
---
src/mesa/drivers/dri/i965/brw_context.h | 1 -
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 +---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 4 +---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 +--
4 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index a4b29fa..6195d3d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -975,7 +975,6 @@ struct brw_context
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
- unsigned mocs,
bool rw);
/**
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 85a08d5..ece352b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -221,7 +221,6 @@ gen4_emit_buffer_surface_state(struct brw_context *brw,
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
- unsigned mocs,
bool rw)
{
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
@@ -279,7 +278,6 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
brw_format,
size / texel_size,
texel_size,
- 0, /* mocs */
false /* rw */);
}
@@ -382,7 +380,7 @@ brw_create_constant_surface(struct brw_context *brw,
brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
- elements, stride, 0, false);
+ elements, stride, false);
}
/**
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index e2c347a..24547d9 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -225,7 +225,6 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
- unsigned mocs,
bool rw)
{
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
@@ -241,7 +240,7 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
(pitch - 1);
- surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
+ surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);
if (brw->is_haswell) {
surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
@@ -385,7 +384,6 @@ gen7_create_raw_surface(struct brw_context *brw,
drm_intel_bo *bo,
BRW_SURFACEFORMAT_RAW,
size,
1,
- 0 /* mocs */,
true /* rw */);
}
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index d1b095c..8d4e180 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -116,9 +116,9 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
- unsigned mocs,
bool rw)
{
+ const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
uint32_t *surf = allocate_surface_state(brw, out_offset);
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
@@ -286,7 +286,6 @@ gen8_create_raw_surface(struct brw_context *brw,
drm_intel_bo *bo,
BRW_SURFACEFORMAT_RAW,
size,
1,
- 0 /* mocs */,
true /* rw */);
}
--
2.1.3
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