This code is complete nonsense and has apparently existed since I first
implemented register spilling in the VS two years ago.
Scratch reads are SEND messages, which ignore the destination writemask.
The comment about "data that may not have been written to scratch" is
also confusing - we always spill whole 4x2 registers, so such data
simply does not exist. We can safely ignore the writemask.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 8 --------
1 file changed, 8 deletions(-)
Apparently no Piglit regressions on Haswell. I did normal before/after
runs, and then also set the "spill everything" option and did a second
set of before/after runs. No changes either way.
(Spilling everything does appear to cause regressions vs. normal
register allocation, though...)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 828a70e..e8e2185 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -335,14 +335,6 @@ vec4_visitor::spill_reg(int spill_reg_nr)
inst->src[i].reg = virtual_grf_alloc(1);
dst_reg temp = dst_reg(inst->src[i]);
- /* Only read the necessary channels, to avoid overwriting the rest
- * with data that may not have been written to scratch.
- */
- temp.writemask = 0;
- for (int c = 0; c < 4; c++)
- temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c));
- assert(temp.writemask != 0);
-
emit_scratch_read(block, inst, temp, spill_reg, spill_offset);
}
}
--
2.1.3
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
