Neither was generated anywhere in the tree. Given that address registers
don't really map as a concept to most hardware these days, we're probably
unlikely to ever extend in the direction of using more address register
opcodes.
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 1 -
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 24 -----------------
src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c | 11 --------
src/gallium/auxiliary/tgsi/tgsi_exec.c | 18 -------------
src/gallium/auxiliary/tgsi/tgsi_info.c | 6 ++---
src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h | 2 --
src/gallium/auxiliary/tgsi/tgsi_util.c | 1 -
src/gallium/docs/source/tgsi.rst | 21 ---------------
src/gallium/drivers/ilo/shader/toy_tgsi.c | 5 ----
src/gallium/drivers/r300/r300_tgsi_to_rc.c | 2 --
src/gallium/drivers/r600/r600_shader.c | 31 +++++-----------------
src/gallium/include/pipe/p_shader_tokens.h | 3 +--
12 files changed, 9 insertions(+), 116 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
index 4a9ce37..44a44a6 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
@@ -212,7 +212,6 @@ lp_build_tgsi_inst_llvm(
case TGSI_OPCODE_UP4B:
case TGSI_OPCODE_UP4UB:
case TGSI_OPCODE_X2D:
- case TGSI_OPCODE_ARA:
case TGSI_OPCODE_BRA:
case TGSI_OPCODE_PUSHA:
case TGSI_OPCODE_POPA:
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index 722aa9a..5daa028 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -96,18 +96,6 @@ add_emit(
emit_data->args[0], emit_data->args[1], "");
}
-/* TGSI_OPCODE_ARR */
-static void
-arr_emit(
- const struct lp_build_tgsi_action * action,
- struct lp_build_tgsi_context * bld_base,
- struct lp_build_emit_data * emit_data)
-{
- LLVMValueRef tmp = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_ROUND,
emit_data->args[0]);
- emit_data->output[emit_data->chan] =
LLVMBuildFPToSI(bld_base->base.gallivm->builder, tmp,
-
bld_base->uint_bld.vec_type, "");
-}
-
/* TGSI_OPCODE_CLAMP */
static void
clamp_emit(
@@ -948,7 +936,6 @@ lp_set_default_actions(struct lp_build_tgsi_context *
bld_base)
bld_base->op_actions[TGSI_OPCODE_LG2].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_ADD].emit = add_emit;
- bld_base->op_actions[TGSI_OPCODE_ARR].emit = arr_emit;
bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = clamp_emit;
bld_base->op_actions[TGSI_OPCODE_END].emit = end_emit;
bld_base->op_actions[TGSI_OPCODE_FRC].emit = frc_emit;
@@ -1028,16 +1015,6 @@ arl_emit_cpu(
bld_base->uint_bld.vec_type, "");
}
-/* TGSI_OPCODE_ARR (CPU Only) */
-static void
-arr_emit_cpu(
- const struct lp_build_tgsi_action * action,
- struct lp_build_tgsi_context * bld_base,
- struct lp_build_emit_data * emit_data)
-{
- emit_data->output[emit_data->chan] = lp_build_iround(&bld_base->base,
emit_data->args[0]);
-}
-
/* TGSI_OPCODE_CEIL (CPU Only) */
static void
ceil_emit_cpu(
@@ -1843,7 +1820,6 @@ lp_set_default_actions_cpu(
bld_base->op_actions[TGSI_OPCODE_ADD].emit = add_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_AND].emit = and_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_ARL].emit = arl_emit_cpu;
- bld_base->op_actions[TGSI_OPCODE_ARR].emit = arr_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_CEIL].emit = ceil_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_CND].emit = cnd_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_COS].emit = cos_emit_cpu;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
index 3b9833a..4af96c1 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
@@ -798,17 +798,6 @@ lp_emit_instruction_aos(
return FALSE;
break;
- case TGSI_OPCODE_ARA:
- /* deprecated */
- assert(0);
- return FALSE;
- break;
-
- case TGSI_OPCODE_ARR:
- src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
- dst0 = lp_build_round(&bld->bld_base.base, src0);
- break;
-
case TGSI_OPCODE_BRA:
/* deprecated */
assert(0);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index b3ea82f..5b9d820 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -93,16 +93,6 @@ micro_arl(union tgsi_exec_channel *dst,
}
static void
-micro_arr(union tgsi_exec_channel *dst,
- const union tgsi_exec_channel *src)
-{
- dst->i[0] = (int)floorf(src->f[0] + 0.5f);
- dst->i[1] = (int)floorf(src->f[1] + 0.5f);
- dst->i[2] = (int)floorf(src->f[2] + 0.5f);
- dst->i[3] = (int)floorf(src->f[3] + 0.5f);
-}
-
-static void
micro_ceil(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src)
{
@@ -3912,14 +3902,6 @@ exec_instruction(
exec_x2d(mach, inst);
break;
- case TGSI_OPCODE_ARA:
- assert (0);
- break;
-
- case TGSI_OPCODE_ARR:
- exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT,
TGSI_EXEC_DATA_FLOAT);
- break;
-
case TGSI_OPCODE_BRA:
assert (0);
break;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index d17426f..efdebbd 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -97,8 +97,8 @@ static const struct tgsi_opcode_info
opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, COMP, "UP4B", TGSI_OPCODE_UP4B },
{ 1, 1, 0, 0, 0, 0, COMP, "UP4UB", TGSI_OPCODE_UP4UB },
{ 1, 3, 0, 0, 0, 0, COMP, "X2D", TGSI_OPCODE_X2D },
- { 1, 1, 0, 0, 0, 0, COMP, "ARA", TGSI_OPCODE_ARA },
- { 1, 1, 0, 0, 0, 0, COMP, "ARR", TGSI_OPCODE_ARR },
+ { 0, 1, 0, 0, 0, 1, NONE, "", 60 }, /* removed */
+ { 0, 1, 0, 0, 0, 1, NONE, "", 61 }, /* removed */
{ 0, 1, 0, 0, 0, 0, NONE, "BRA", TGSI_OPCODE_BRA },
{ 0, 0, 0, 1, 0, 0, NONE, "CAL", TGSI_OPCODE_CAL },
{ 0, 0, 0, 0, 0, 0, NONE, "RET", TGSI_OPCODE_RET },
@@ -316,7 +316,6 @@ tgsi_opcode_infer_type( uint opcode )
case TGSI_OPCODE_UMUL_HI:
return TGSI_TYPE_UNSIGNED;
case TGSI_OPCODE_ARL:
- case TGSI_OPCODE_ARR:
case TGSI_OPCODE_MOD:
case TGSI_OPCODE_F2I:
case TGSI_OPCODE_FSEQ:
@@ -363,7 +362,6 @@ tgsi_opcode_infer_src_type( uint opcode )
case TGSI_OPCODE_I2F:
return TGSI_TYPE_SIGNED;
case TGSI_OPCODE_ARL:
- case TGSI_OPCODE_ARR:
case TGSI_OPCODE_TXQ_LZ:
case TGSI_OPCODE_F2I:
case TGSI_OPCODE_F2U:
diff --git a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
index b121d32..97ac364 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
@@ -112,8 +112,6 @@ OP11(UP2US)
OP11(UP4B)
OP11(UP4UB)
OP13(X2D)
-OP11(ARA)
-OP11(ARR)
OP01(BRA)
OP00_LBL(CAL)
OP00(RET)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c
b/src/gallium/auxiliary/tgsi/tgsi_util.c
index 66cb167..916a5be 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_util.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_util.c
@@ -181,7 +181,6 @@ tgsi_util_get_inst_usage_mask(const struct
tgsi_full_instruction *inst,
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_MOV:
case TGSI_OPCODE_ARL:
- case TGSI_OPCODE_ARR:
case TGSI_OPCODE_RCP:
case TGSI_OPCODE_MUL:
case TGSI_OPCODE_DIV:
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index c912ec5..a4405f1 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -701,27 +701,6 @@ This instruction replicates its result.
Considered for removal.
-.. opcode:: ARA - Address Register Add
-
- TBD
-
-.. note::
-
- Considered for removal.
-
-.. opcode:: ARR - Address Register Load With Round
-
-.. math::
-
- dst.x = round(src.x)
-
- dst.y = round(src.y)
-
- dst.z = round(src.z)
-
- dst.w = round(src.w)
-
-
.. opcode:: SSG - Set Sign
.. math::
diff --git a/src/gallium/drivers/ilo/shader/toy_tgsi.c
b/src/gallium/drivers/ilo/shader/toy_tgsi.c
index 1bf9f21..4fd8412 100644
--- a/src/gallium/drivers/ilo/shader/toy_tgsi.c
+++ b/src/gallium/drivers/ilo/shader/toy_tgsi.c
@@ -63,7 +63,6 @@ static const struct {
[TGSI_OPCODE_COS] = { TOY_OPCODE_COS, 1, 1 },
[TGSI_OPCODE_KILL] = { TOY_OPCODE_KIL, 0, 0 },
[TGSI_OPCODE_SIN] = { TOY_OPCODE_SIN, 1, 1 },
- [TGSI_OPCODE_ARR] = { GEN6_OPCODE_RNDZ, 1, 1 },
[TGSI_OPCODE_DP2] = { GEN6_OPCODE_DP2, 1, 2 },
[TGSI_OPCODE_IF] = { GEN6_OPCODE_IF, 0, 1 },
[TGSI_OPCODE_UIF] = { GEN6_OPCODE_IF, 0, 1 },
@@ -854,8 +853,6 @@ static const toy_tgsi_translate
aos_translate_table[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_UP4B] = aos_unsupported,
[TGSI_OPCODE_UP4UB] = aos_unsupported,
[TGSI_OPCODE_X2D] = aos_unsupported,
- [TGSI_OPCODE_ARA] = aos_unsupported,
- [TGSI_OPCODE_ARR] = aos_simple,
[TGSI_OPCODE_BRA] = aos_unsupported,
[TGSI_OPCODE_CAL] = aos_unsupported,
[TGSI_OPCODE_RET] = aos_unsupported,
@@ -1404,8 +1401,6 @@ static const toy_tgsi_translate
soa_translate_table[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_UP4B] = soa_unsupported,
[TGSI_OPCODE_UP4UB] = soa_unsupported,
[TGSI_OPCODE_X2D] = soa_unsupported,
- [TGSI_OPCODE_ARA] = soa_unsupported,
- [TGSI_OPCODE_ARR] = soa_per_channel,
[TGSI_OPCODE_BRA] = soa_unsupported,
[TGSI_OPCODE_CAL] = soa_unsupported,
[TGSI_OPCODE_RET] = soa_unsupported,
diff --git a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
index f371713..b70a38c 100644
--- a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
+++ b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
@@ -87,8 +87,6 @@ static unsigned translate_opcode(unsigned opcode)
/* case TGSI_OPCODE_UP4B: return RC_OPCODE_UP4B; */
/* case TGSI_OPCODE_UP4UB: return RC_OPCODE_UP4UB; */
/* case TGSI_OPCODE_X2D: return RC_OPCODE_X2D; */
- /* case TGSI_OPCODE_ARA: return RC_OPCODE_ARA; */
- /* case TGSI_OPCODE_ARR: return RC_OPCODE_ARR; */
/* case TGSI_OPCODE_BRA: return RC_OPCODE_BRA; */
/* case TGSI_OPCODE_CAL: return RC_OPCODE_CAL; */
/* case TGSI_OPCODE_RET: return RC_OPCODE_RET; */
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 4d87a29..bc29c2e 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -6502,9 +6502,6 @@ static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
case TGSI_OPCODE_ARL:
alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
break;
- case TGSI_OPCODE_ARR:
- alu.op = ALU_OP1_FLT_TO_INT;
- break;
case TGSI_OPCODE_UARL:
alu.op = ALU_OP1_MOV;
break;
@@ -6570,22 +6567,6 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
return r;
}
break;
- case TGSI_OPCODE_ARR:
- memset(&alu, 0, sizeof(alu));
- alu.op = ALU_OP1_FLT_TO_INT;
- alu.dst.sel = ctx->bc->ar_reg;
- alu.dst.write = 1;
- /* FLT_TO_INT is trans-only on r600/r700 */
- alu.last = TRUE;
- for (i = 0; i <= lasti; ++i) {
- if (inst->Dst[0].Register.WriteMask & (1 << i)) {
- alu.dst.chan = i;
- r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
- }
- }
- break;
case TGSI_OPCODE_UARL:
memset(&alu, 0, sizeof(alu));
alu.op = ALU_OP1_MOV;
@@ -7194,8 +7175,8 @@ static struct r600_shader_tgsi_instruction
r600_shader_tgsi_instruction[] = {
{TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
- {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
- {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
+ {60, 0, ALU_OP0_NOP, tgsi_unsupported},
+ {61, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
@@ -7393,8 +7374,8 @@ static struct r600_shader_tgsi_instruction
eg_shader_tgsi_instruction[] = {
{TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
- {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
- {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
+ {60, 0, ALU_OP0_NOP, tgsi_unsupported},
+ {61, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
@@ -7592,8 +7573,8 @@ static struct r600_shader_tgsi_instruction
cm_shader_tgsi_instruction[] = {
{TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
- {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
- {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
+ {60, 0, ALU_OP0_NOP, tgsi_unsupported},
+ {61, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
diff --git a/src/gallium/include/pipe/p_shader_tokens.h
b/src/gallium/include/pipe/p_shader_tokens.h
index b1e7b10..05b6fc1 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -343,8 +343,7 @@ struct tgsi_property_data {
#define TGSI_OPCODE_UP4B 57
#define TGSI_OPCODE_UP4UB 58
#define TGSI_OPCODE_X2D 59
-#define TGSI_OPCODE_ARA 60
-#define TGSI_OPCODE_ARR 61
+ /* gap */
#define TGSI_OPCODE_BRA 62
#define TGSI_OPCODE_CAL 63
#define TGSI_OPCODE_RET 64
--
2.1.1
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