On Oct 8, 2014 11:39 AM, "Connor Abbott" <cwabbo...@gmail.com> wrote:
>
> On Tue, Oct 7, 2014 at 4:33 AM, Jason Ekstrand <ja...@jlekstrand.net>
wrote:
> > On older GENs in SIMD16 mode, we were accidentally building too much
> > interference into our register classes. Since everything is divided by
2,
> > the reigster allocator thinks we have 64 base registers instead of 128.
> > The actual GRF mapping still needs to be doubled, but as far as the
ra_set
> > is concerned, we only have 64. We were accidentally adding way too much
> > interference.
>
> Hmm, interesting. I'm not sure I quite follow the logic yet, but I
> trust you that this is the right thing. Btw, just for the lols, did
> you try and run shaderdb on this change? I bet we'd allocate even more
> things on SIMD16 :) The SIMD16 register allocator saga continues, I
> guess...
Until my desktop shows up, running shader-db is never for LOLs. It takes
20 minutes per run on my poor thermally throttled ultrabook. But yes, the
results would be amusing.
> >
> > Signed-off-by: Jason Ekstrand <jason.ekstr...@gmail.com>
> > Cc: Connor Abbot <cwabbo...@gmail.com>
> > ---
> > src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> > index fd34941..b23ddc5 100644
> > --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> > @@ -179,8 +179,8 @@ brw_alloc_reg_set(struct intel_screen *screen, int
reg_width)
> >
> > ra_reg_to_grf[reg] = j * 2;
> >
> > - for (int base_reg = j * 2;
> > - base_reg < j * 2 + class_sizes[i];
> > + for (int base_reg = j;
> > + base_reg < j + (class_sizes[i] + 1) / 2;
> > base_reg++) {
> > ra_add_transitive_reg_conflict(regs, base_reg, reg);
> > }
> > --
> > 2.1.0
> >
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