On Fri, Sep 26, 2014 at 4:09 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> ~0 is 0xFFFFFFFF, which only covers the first 32 bits. We need all 64.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
> src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_state_cache.c | 2 +-
> src/mesa/drivers/dri/i965/brw_state_upload.c | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> I think Jordan/Paul fixed this with macros, but we reverted that patch.
> This fixes it in the minimal way; we can think about adding macros later.
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
> b/src/mesa/drivers/dri/i965/brw_blorp.cpp
> index 2c00bce..20ce7b7 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
> @@ -276,7 +276,7 @@ retry:
> /* We've smashed all state compared to what the normal 3D pipeline
> * rendering tracks for GL.
> */
> - brw->state.dirty.brw = ~0;
> + brw->state.dirty.brw = ~0ull;
> brw->state.dirty.cache = ~0;
> brw->no_depth_or_stencil = false;
> brw->ib.type = -1;
> diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c
> b/src/mesa/drivers/dri/i965/brw_state_cache.c
> index 882d131..62e03b1 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_cache.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
> @@ -379,7 +379,7 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache
> *cache)
> * any offsets leftover in brw_context will no longer be valid.
> */
> brw->state.dirty.mesa |= ~0;
> - brw->state.dirty.brw |= ~0;
> + brw->state.dirty.brw |= ~0ull;
> brw->state.dirty.cache |= ~0;
> intel_batchbuffer_flush(brw);
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index e124ce4..9e3cfb8 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -388,7 +388,7 @@ void brw_init_state( struct brw_context *brw )
> brw_upload_initial_gpu_state(brw);
>
> brw->state.dirty.mesa = ~0;
> - brw->state.dirty.brw = ~0;
> + brw->state.dirty.brw = ~0ull;
>
> /* Make sure that brw->state.dirty.brw has enough bits to hold all
> possible
> * dirty flags.
> @@ -575,7 +575,7 @@ void brw_upload_state(struct brw_context *brw)
> if (0) {
> /* Always re-emit all state. */
> state->mesa |= ~0;
> - state->brw |= ~0;
> + state->brw |= ~0ull;
> state->cache |= ~0;
Something stupid about ORing with a field-width set of 1s, but that's
how the code is.
Looks good to me. The whole series is
Reviewed-by: Matt Turner <matts...@gmail.com>
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