Assuming my half-dozen comments are addressed, 5-14 are Reviewed-by: Jason Ekstrand <jason.ekstr...@intel.com>
On Thu, Aug 28, 2014 at 8:10 PM, Matt Turner <matts...@gmail.com> wrote: > --- > src/mesa/drivers/dri/i965/brw_eu_compact.c | 35 > ++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c > b/src/mesa/drivers/dri/i965/brw_eu_compact.c > index e9ba928..38a60d0 100644 > --- a/src/mesa/drivers/dri/i965/brw_eu_compact.c > +++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c > @@ -35,6 +35,41 @@ > * The idea of instruction compaction is that most instructions use a tiny > * subset of the GPU functionality, so we can encode what would be a 16 > byte > * instruction in 8 bytes using some lookup tables for various fields. > + * > + * > + * Instruction compaction capabilities vary subtly by generation. > + * > + * G45's support for instruction compaction is very limited. Jump counts > on > + * this generation are in units of 16-byte uncompacted instructions. As > such, > + * all jump targets must be 16-byte aligned. Also, all instructions must > be > + * naturally aligned, i.e. uncompacted instructions must be 16-byte > aligned. > + * A G45-only instruction, NENOP, must be used to provide padding to align > + * uncompacted instructions. > + * > + * Gen5 removes these restrictions and changes jump counts to be in units > of > + * 8-byte compacted instructions, allowing jump targets to be only 8-byte > + * aligned. Uncompacted instructions can also be placed on 8-byte > boundaries. > + * > + * Gen6 adds the ability to compact instructions with a limited range of > + * immediate values. Compactable immediates have 12 unrestricted bits, > and a > + * 13th bit that's replicated through the high 20 bits, to create the > 32-bit > + * value of DW3 in the uncompacted instruction word. > + * > + * On Gen7 we can compact some control flow instructions with a small > positive > + * immediate in the low bits of DW3, like ENDIF with the JIP field. Other > + * control flow instructions with UIP cannot be compacted, because of the > + * replicated 13th bit. No control flow instructions can be compacted on > Gen6 > + * since the jump count field is not in DW3. > + * > + * break JIP/UIP > + * cont JIP/UIP > + * halt JIP/UIP > + * if JIP/UIP > + * else JIP (plus UIP on BDW+) > + * endif JIP > + * while JIP (must be negative) > + * > + * Gen 8 adds support for compacting 3-src instructions. > */ > > #include "brw_context.h" > -- > 1.8.5.5 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev >
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