---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 5617947..dd32175 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -737,6 +737,8 @@ brw_try_compact_instruction(struct brw_context *brw,
brw_compact_inst *dst,
{
brw_compact_inst temp;
+ assert(brw_inst_cmpt_control(brw, src) == 0);
+
if (brw_inst_opcode(brw, src) == BRW_OPCODE_IF ||
brw_inst_opcode(brw, src) == BRW_OPCODE_ELSE ||
brw_inst_opcode(brw, src) == BRW_OPCODE_ENDIF ||
@@ -1105,10 +1107,10 @@ brw_compact_instructions(struct brw_compile *p, int
start_offset,
if (brw->gen < 6)
return;
- int src_offset;
int offset = 0;
int compacted_count = 0;
- for (src_offset = 0; src_offset < p->next_insn_offset - start_offset;) {
+ for (int src_offset = 0; src_offset < p->next_insn_offset - start_offset;
+ src_offset += sizeof(brw_inst)) {
brw_inst *src = store + src_offset;
void *dst = store + offset;
@@ -1117,8 +1119,7 @@ brw_compact_instructions(struct brw_compile *p, int
start_offset,
brw_inst saved = *src;
- if (!brw_inst_cmpt_control(brw, src) &&
- brw_try_compact_instruction(brw, dst, src)) {
+ if (brw_try_compact_instruction(brw, dst, src)) {
compacted_count++;
if (INTEL_DEBUG) {
@@ -1130,10 +1131,7 @@ brw_compact_instructions(struct brw_compile *p, int
start_offset,
}
offset += 8;
- src_offset += 16;
} else {
- int size = brw_inst_cmpt_control(brw, src) ? 8 : 16;
-
/* It appears that the end of thread SEND instruction needs to be
* aligned, or the GPU hangs.
*/
@@ -1154,10 +1152,9 @@ brw_compact_instructions(struct brw_compile *p, int
start_offset,
* place.
*/
if (offset != src_offset) {
- memmove(dst, src, size);
+ memmove(dst, src, sizeof(brw_inst));
}
- offset += size;
- src_offset += size;
+ offset += sizeof(brw_inst);
}
}
--
1.8.5.5
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