r-b with these changes?
By the way, chrisf pointed out on irc that we should extend
ctx->NewDriverState to 64-bit as well. I'll look into that, but I
don't think it needs to block this change. Although, I'd be willing to
pull that in here as well if anyone prefers it.
-Jordan
On Wed, Aug 27, 2014 at 3:16 PM, Ian Romanick <i...@freedesktop.org> wrote:
> On 08/27/2014 02:30 PM, Jordan Justen wrote:
>> We will have more that 32 bits when COMPUTE_PROGRAM is added.
>>
>> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
>> ---
>> src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +-
>> src/mesa/drivers/dri/i965/brw_context.h | 16 +++++++++++++++-
>> src/mesa/drivers/dri/i965/brw_state_cache.c | 2 +-
>> src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +-
>> 4 files changed, 18 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
>> b/src/mesa/drivers/dri/i965/brw_blorp.cpp
>> index c5cc823..17ae2bf 100644
>> --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
>> @@ -273,7 +273,7 @@ retry:
>> /* We've smashed all state compared to what the normal 3D pipeline
>> * rendering tracks for GL.
>> */
>> - SET_DIRTY_ALL(brw);
>> + SET_DIRTY64_ALL(brw);
>> SET_DIRTY_ALL(cache);
>> brw->no_depth_or_stencil = false;
>> brw->ib.type = -1;
>> diff --git a/src/mesa/drivers/dri/i965/brw_context.h
>> b/src/mesa/drivers/dri/i965/brw_context.h
>> index 7b2eea1..875c43b 100644
>> --- a/src/mesa/drivers/dri/i965/brw_context.h
>> +++ b/src/mesa/drivers/dri/i965/brw_context.h
>> @@ -229,7 +229,7 @@ struct brw_state_flags {
>> /**
>> * State update flags signalled as the result of brw_tracked_state
>> updates
>> */
>> - GLuint brw;
>> + GLuint64 brw;
>
> I'd take this opportunity to get rid of the GL type. Make this uint64_t
> instead.
>
>> /**
>> * State update flags that used to be signalled by brw_state_cache.c
>> * searches.
>> @@ -287,6 +287,20 @@ typedef enum {
>>
>>
>> /**
>> + * Set all of the bits in a field of brw_state_flags.
>> + */
>> +#define SET_DIRTY64_ALL(FIELD) \
>> + do { \
>> + int which_pipeline; \
>
> Same comment about C99 as a previous patch.
>
>> + /* ~0 == 0xffffffff, so make sure field is <= 32 bits */ \
>
> This comment seems... stale. :)
>
>> + STATIC_ASSERT(sizeof(brw->state.pipeline_dirty[0].FIELD) == 8); \
>> + for (which_pipeline = 0; which_pipeline < BRW_NUM_PIPELINES; \
>> + which_pipeline++) \
>> + brw->state.pipeline_dirty[which_pipeline].FIELD = ~(0ULL); \
>> + } while (false)
>> +
>> +
>> +/**
>> * Check one of the bits in a field of brw_state_flags.
>> */
>> #define CHECK_DIRTY_BIT(FIELD, FLAG) \
>> diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c
>> b/src/mesa/drivers/dri/i965/brw_state_cache.c
>> index fcb7277..19079c8 100644
>> --- a/src/mesa/drivers/dri/i965/brw_state_cache.c
>> +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
>> @@ -380,7 +380,7 @@ brw_clear_cache(struct brw_context *brw, struct
>> brw_cache *cache)
>> * any offsets leftover in brw_context will no longer be valid.
>> */
>> SET_DIRTY_ALL(mesa);
>> - SET_DIRTY_ALL(brw);
>> + SET_DIRTY64_ALL(brw);
>> SET_DIRTY_ALL(cache);
>> intel_batchbuffer_flush(brw);
>> }
>> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
>> b/src/mesa/drivers/dri/i965/brw_state_upload.c
>> index 3022ab1..9d93431 100644
>> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
>> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
>> @@ -391,7 +391,7 @@ void brw_init_state( struct brw_context *brw )
>> brw_upload_initial_gpu_state(brw);
>>
>> SET_DIRTY_ALL(mesa);
>> - SET_DIRTY_ALL(brw);
>> + SET_DIRTY64_ALL(brw);
>>
>> /* Make sure that brw->state.dirty.brw has enough bits to hold all
>> possible
>> * dirty flags.
>>
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
