Prepares for merging common bits of gen7/8 renderbuffer surface setup.
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 12 ++++++------
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 9d9aa1c..58ce614 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -243,7 +243,7 @@ int brw_get_texture_swizzle(const struct gl_context *ctx,
/* gen7_wm_surface_state.c */
unsigned brw_swizzle_to_scs(GLenum swizzle, bool need_green_to_blue);
-uint32_t gen7_surface_tiling_mode(uint32_t tiling);
+uint32_t gen7_surface_tiling_mode(int gen, uint32_t tiling);
uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout
l);
void gen7_set_surface_mcs_info(struct brw_context *brw,
uint32_t *surf,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 9c87886..99c46bb 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -162,7 +162,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
- gen7_surface_tiling_mode(tiling);
+ gen7_surface_tiling_mode(brw->gen, tiling);
if (surface->mt->align_h == 4)
surf[0] |= GEN7_SURFACE_VALIGN_4;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index f2b6382..be10d5d 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -63,15 +63,15 @@ brw_swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
}
uint32_t
-gen7_surface_tiling_mode(uint32_t tiling)
+gen7_surface_tiling_mode(int gen, uint32_t tiling)
{
switch (tiling) {
case I915_TILING_X:
- return GEN7_SURFACE_TILING_X;
+ return gen >= 8 ? GEN8_SURFACE_TILING_X : GEN7_SURFACE_TILING_X;
case I915_TILING_Y:
- return GEN7_SURFACE_TILING_Y;
+ return gen >= 8 ? GEN8_SURFACE_TILING_Y : GEN7_SURFACE_TILING_Y;
default:
- return GEN7_SURFACE_TILING_NONE;
+ return gen >= 8 ? GEN8_SURFACE_TILING_NONE : GEN7_SURFACE_TILING_NONE;
}
}
@@ -295,7 +295,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
tex_format << BRW_SURFACE_FORMAT_SHIFT |
- gen7_surface_tiling_mode(mt->tiling);
+ gen7_surface_tiling_mode(brw->gen, mt->tiling);
/* mask of faces present in cube map; for other surfaces MBZ. */
if (tObj->Target == GL_TEXTURE_CUBE_MAP || tObj->Target ==
GL_TEXTURE_CUBE_MAP_ARRAY)
@@ -491,7 +491,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
format << BRW_SURFACE_FORMAT_SHIFT |
(irb->mt->non_mip_arrays ? GEN7_SURFACE_ARYSPC_LOD0
: GEN7_SURFACE_ARYSPC_FULL) |
- gen7_surface_tiling_mode(mt->tiling);
+ gen7_surface_tiling_mode(brw->gen, mt->tiling);
if (irb->mt->align_h == 4)
surf[0] |= GEN7_SURFACE_VALIGN_4;
--
1.8.3.1
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