Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/gen6_depth_state.c | 6 +-----
src/mesa/drivers/dri/i965/gen6_surface_state.c | 3 +--
src/mesa/drivers/dri/i965/gen7_misc_state.c | 10 +---------
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 6 +-----
src/mesa/drivers/dri/i965/gen8_depth_state.c | 10 +---------
src/mesa/drivers/dri/i965/gen8_surface_state.c | 6 +-----
src/mesa/drivers/dri/i965/intel_fbo.h | 14 ++++++++++++++
7 files changed, 20 insertions(+), 35 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 1a8df99..7c8c87e 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -47,7 +47,6 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
struct gl_context *ctx = &brw->ctx;
struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t surftype;
- unsigned int depth = 1;
unsigned int min_array_element;
unsigned int lod;
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
@@ -80,9 +79,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
rb = (struct gl_renderbuffer*) irb;
const GLenum gl_target = brw_get_target(rb);
-
- if (rb)
- depth = MAX2(rb->Depth, 1);
+ const unsigned depth = intel_rb_adjust_depth(brw, irb, mt, gl_target);
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -93,7 +90,6 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
* equivalent.
*/
surftype = BRW_SURFACE_2D;
- depth *= 6;
break;
default:
surftype = translate_tex_target(gl_target);
diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c
b/src/mesa/drivers/dri/i965/gen6_surface_state.c
index ef13d3d..c1c4c47 100644
--- a/src/mesa/drivers/dri/i965/gen6_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c
@@ -59,8 +59,8 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
const GLenum gl_target = brw_get_target(rb);
+ const int depth = intel_rb_adjust_depth(brw, irb, mt, gl_target);
uint32_t surftype;
- int depth = MAX2(rb->Depth, 1);
uint32_t surf_index =
brw->wm.prog_data->binding_table.render_target_start + unit;
@@ -80,7 +80,6 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
case GL_TEXTURE_CUBE_MAP_ARRAY:
case GL_TEXTURE_CUBE_MAP:
surftype = BRW_SURFACE_2D;
- depth *= 6;
break;
default:
surftype = translate_tex_target(gl_target);
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 1419364..68fa89c 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -43,7 +43,6 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
const uint8_t mocs = GEN7_MOCS_L3;
struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t surftype;
- unsigned int depth = 1;
unsigned int min_array_element;
unsigned int lod;
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
@@ -64,9 +63,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
rb = (struct gl_renderbuffer*) irb;
const GLenum gl_target = brw_get_target(rb);
-
- if (rb)
- depth = MAX2(irb->layer_count, 1);
+ const unsigned depth = intel_rb_adjust_depth(brw, irb, mt, gl_target);
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -77,12 +74,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
* equivalent.
*/
surftype = BRW_SURFACE_2D;
- depth *= 6;
break;
- case GL_TEXTURE_3D:
- assert(mt);
- depth = MAX2(mt->logical_depth0, 1);
- /* fallthrough */
default:
surftype = translate_tex_target(gl_target);
break;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 89d92ab..8112a8e 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -462,9 +462,9 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
const GLenum gl_target = brw_get_target(rb);
+ const int depth = intel_rb_adjust_depth(brw, irb, mt, gl_target);
uint32_t surftype;
bool is_array = false;
- int depth = MAX2(irb->layer_count, 1);
const uint8_t mocs = GEN7_MOCS_L3;
int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
@@ -493,11 +493,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
case GL_TEXTURE_CUBE_MAP:
surftype = BRW_SURFACE_2D;
is_array = true;
- depth *= 6;
break;
- case GL_TEXTURE_3D:
- depth = MAX2(irb->mt->logical_depth0, 1);
- /* fallthrough */
default:
surftype = translate_tex_target(gl_target);
is_array = _mesa_tex_target_is_array(gl_target);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 96e722b..61daf24 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -154,7 +154,6 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
struct gl_context *ctx = &brw->ctx;
struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t surftype;
- unsigned int depth = 1;
unsigned int min_array_element;
unsigned int lod;
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
@@ -167,9 +166,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
rb = (struct gl_renderbuffer *) irb;
const GLenum gl_target = brw_get_target(rb);
-
- if (rb)
- depth = MAX2(irb->layer_count, 1);
+ const unsigned depth = intel_rb_adjust_depth(brw, irb, mt, gl_target);
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -180,12 +177,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
* equivalent.
*/
surftype = BRW_SURFACE_2D;
- depth *= 6;
break;
- case GL_TEXTURE_3D:
- assert(mt);
- depth = MAX2(mt->logical_depth0, 1);
- /* fallthrough */
default:
surftype = translate_tex_target(gl_target);
break;
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 5575aa4..8ce382c 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -310,6 +310,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
struct intel_mipmap_tree *mt = irb->mt;
struct intel_mipmap_tree *aux_mt = NULL;
const GLenum gl_target = brw_get_target(rb);
+ const int depth = intel_rb_adjust_depth(brw, irb, mt, gl_target);
uint32_t aux_mode = 0;
unsigned width = mt->logical_width0;
unsigned height = mt->logical_height0;
@@ -318,7 +319,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
uint32_t format = 0;
uint32_t surf_type;
bool is_array = false;
- int depth = MAX2(irb->layer_count, 1);
const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
@@ -332,11 +332,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
case GL_TEXTURE_CUBE_MAP:
surf_type = BRW_SURFACE_2D;
is_array = true;
- depth *= 6;
break;
- case GL_TEXTURE_3D:
- depth = MAX2(irb->mt->logical_depth0, 1);
- /* fallthrough */
default:
surf_type = translate_tex_target(gl_target);
is_array = _mesa_tex_target_is_array(gl_target);
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h
b/src/mesa/drivers/dri/i965/intel_fbo.h
index c7cc570..0d78e17 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -171,6 +171,20 @@ intel_rb_format(const struct intel_renderbuffer *rb)
return rb->Base.Base.Format;
}
+static inline unsigned
+intel_rb_adjust_depth(const struct brw_context *brw,
+ const struct intel_renderbuffer *irb,
+ const struct intel_mipmap_tree *mt,
+ GLenum gl_target)
+{
+ if (brw->gen >= 7 && gl_target == GL_TEXTURE_3D) {
+ assert(mt);
+ return MAX2(mt->logical_depth0, 1);
+ }
+
+ return brw_adjust_depth(irb ? irb->layer_count : 1, gl_target);
+}
+
extern struct intel_renderbuffer *
intel_create_renderbuffer(mesa_format format, unsigned num_samples);
--
1.8.3.1
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