On Tue, Jul 15, 2014 at 06:32:17PM -0700, Jordan Justen wrote:
> For hiz, the qpitch may be different than the main miptree.
s/hiz/aux/ ?
>
> In "i965: Wrap MCS miptree in intel_miptree_aux_buffer" we set
> aux_buf->qpitch to mt->qpitch, so for MCS, this should be a no-op.
>
> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
> ---
> src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index 87f0d49..3d97232 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -203,7 +203,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
> (intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
>
> if (aux_buf) {
> - surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
> + surf[6] = SET_FIELD(aux_buf->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
> SET_FIELD((aux_buf->pitch / 128) - 1,
> GEN8_SURFACE_AUX_PITCH) |
> aux_mode;
> } else {
> @@ -394,7 +394,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
> surf[5] = irb->mt_level - irb->mt->first_level;
>
> if (aux_buf) {
> - surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
> + surf[6] = SET_FIELD(aux_buf->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
> SET_FIELD((aux_buf->pitch / 128) - 1,
> GEN8_SURFACE_AUX_PITCH) |
> aux_mode;
> } else {
> --
> 2.0.0
>
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