Everything is in place and appears to be working.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e4d67b9..a45f1dd 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -68,14 +68,6 @@ compute_msaa_layout(struct brw_context *brw, mesa_format
format, GLenum target)
case GL_DEPTH_STENCIL:
return INTEL_MSAA_LAYOUT_IMS;
default:
- /* Disable MCS on Broadwell for now. We can enable it once things
- * are working without it.
- */
- if (brw->gen >= 8) {
- perf_debug("Missing CMS support on Broadwell.\n");
- return INTEL_MSAA_LAYOUT_UMS;
- }
-
/* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
*
* This field must be set to 0 for all SINT MSRTs when all RT channels
--
2.0.0
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