Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 15 +++++++++++++
src/mesa/drivers/dri/i965/gen7_misc_state.c | 26 ++---------------------
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 +-----------
4 files changed, 19 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 407f233..9e7df9f 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -221,6 +221,7 @@ brw_is_array(GLenum target)
void gen4_init_vtable_surface_functions(struct brw_context *brw);
uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
uint32_t brw_get_surface_type(GLenum gl_target);
+int brw_get_depth(struct gl_renderbuffer *rb);
uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
void brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 4cc3f49..82c7978 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -109,6 +109,21 @@ brw_get_surface_type(const GLenum gl_target)
}
}
+int
+brw_get_depth(struct gl_renderbuffer *rb)
+{
+ const GLenum target = brw_get_target(rb);
+ const struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+ if (target == GL_TEXTURE_3D)
+ return MAX2(irb->mt->logical_depth0, 1);
+
+ if (target == GL_TEXTURE_CUBE_MAP_ARRAY || target == GL_TEXTURE_CUBE_MAP)
+ return 6 * MAX2(irb->layer_count, 1);
+
+ return MAX2(irb->layer_count, 1);
+}
+
uint32_t
brw_get_surface_num_multisamples(unsigned num_samples)
{
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 870e2c7..31bb124 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -42,12 +42,11 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
struct gl_context *ctx = &brw->ctx;
const uint8_t mocs = GEN7_MOCS_L3;
struct gl_framebuffer *fb = ctx->DrawBuffer;
- unsigned int depth = 1;
unsigned int min_array_element;
unsigned int lod;
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
const struct intel_renderbuffer *irb = NULL;
- const struct gl_renderbuffer *rb = NULL;
+ struct gl_renderbuffer *rb = NULL;
/* Skip repeated NULL depth/stencil emits (think 2D rendering). */
if (!mt && brw->no_depth_or_stencil) {
@@ -62,30 +61,9 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
rb = (struct gl_renderbuffer*) irb;
const GLenum gl_target = rb ? brw_get_target(rb) : GL_TEXTURE_2D;
+ const int depth = rb ? brw_get_depth(rb) : 1;
const uint32_t surftype = brw_get_surface_type(gl_target);
- if (rb) {
- depth = MAX2(irb->layer_count, 1);
- }
-
- switch (gl_target) {
- case GL_TEXTURE_CUBE_MAP_ARRAY:
- case GL_TEXTURE_CUBE_MAP:
- /* The PRM claims that we should use BRW_SURFACE_CUBE for this
- * situation, but experiments show that gl_Layer doesn't work when we do
- * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
- * equivalent.
- */
- depth *= 6;
- break;
- case GL_TEXTURE_3D:
- assert(mt);
- depth = MAX2(mt->logical_depth0, 1);
- /* fallthrough */
- default:
- break;
- }
-
min_array_element = irb ? irb->mt_layer : 0;
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 5d48001..d07a601 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -454,7 +454,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
const GLenum gl_target = brw_get_target(rb);
const uint32_t surftype = brw_get_surface_type(gl_target);
- int depth = MAX2(irb->layer_count, 1);
+ const int depth = brw_get_depth(rb);
const uint8_t mocs = GEN7_MOCS_L3;
int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
@@ -478,18 +478,6 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
__FUNCTION__, _mesa_get_format_name(rb_format));
}
- switch (gl_target) {
- case GL_TEXTURE_CUBE_MAP_ARRAY:
- case GL_TEXTURE_CUBE_MAP:
- depth *= 6;
- break;
- case GL_TEXTURE_3D:
- depth = MAX2(irb->mt->logical_depth0, 1);
- /* fallthrough */
- default:
- break;
- }
-
surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
format << BRW_SURFACE_FORMAT_SHIFT |
(irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
--
1.8.3.1
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