Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_state.h | 9 +++++++++ src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 6 +----- 2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index ee87092..407f233 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -34,6 +34,7 @@ #define BRW_STATE_H #include "brw_context.h" +#include "main/texformat.h" #ifdef __cplusplus extern "C" { @@ -209,6 +210,14 @@ brw_get_target(const struct gl_renderbuffer *rb) return rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; } +inline static bool +brw_is_array(GLenum target) +{ + if (target == GL_TEXTURE_CUBE_MAP_ARRAY || target == GL_TEXTURE_CUBE_MAP) + return true; + return _mesa_tex_target_is_array(target); +} + void gen4_init_vtable_surface_functions(struct brw_context *brw); uint32_t brw_get_surface_tiling_bits(uint32_t tiling); uint32_t brw_get_surface_type(GLenum gl_target); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 3c57535..5d48001 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -454,7 +454,6 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); const GLenum gl_target = brw_get_target(rb); const uint32_t surftype = brw_get_surface_type(gl_target); - bool is_array = false; int depth = MAX2(irb->layer_count, 1); const uint8_t mocs = GEN7_MOCS_L3; @@ -482,14 +481,12 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, switch (gl_target) { case GL_TEXTURE_CUBE_MAP_ARRAY: case GL_TEXTURE_CUBE_MAP: - is_array = true; depth *= 6; break; case GL_TEXTURE_3D: depth = MAX2(irb->mt->logical_depth0, 1); /* fallthrough */ default: - is_array = _mesa_tex_target_is_array(gl_target); break; } @@ -504,9 +501,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, if (irb->mt->align_w == 8) surf[0] |= GEN7_SURFACE_HALIGN_8; - if (is_array) { + if (brw_is_array(gl_target)) surf[0] |= GEN7_SURFACE_IS_ARRAY; - } surf[1] = mt->bo->offset64; -- 1.8.3.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev