v2: Configure stencil directly for final dimensions instead of
adjusting bit by bit for tiling, mip level and msaa.
Cc: "10.2" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> (v1)
---
src/mesa/drivers/dri/i965/brw_context.h | 4 +++
src/mesa/drivers/dri/i965/brw_meta_updownsample.c | 32 ++++++++++++++++++-----
2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 92e1592..6d4a5b5 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1475,6 +1475,10 @@ GLboolean brwCreateContext(gl_api api,
/*======================================================================
* brw_misc_state.c
*/
+GLuint brw_get_rb_for_slice(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ unsigned level, unsigned layer, bool flat);
+
void brw_meta_updownsample(struct brw_context *brw,
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
index de25bf4..3592857 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
@@ -44,8 +44,10 @@
*
* Clobbers the current renderbuffer binding (ctx->CurrentRenderbuffer).
*/
-static GLuint
-brw_get_rb_for_first_slice(struct brw_context *brw, struct intel_mipmap_tree
*mt)
+GLuint
+brw_get_rb_for_slice(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ unsigned level, unsigned layer, bool flat)
{
struct gl_context *ctx = &brw->ctx;
GLuint rbo;
@@ -64,9 +66,25 @@ brw_get_rb_for_first_slice(struct brw_context *brw, struct
intel_mipmap_tree *mt
rb->Format = mt->format;
rb->_BaseFormat = _mesa_base_fbo_format(ctx, mt->format);
- rb->NumSamples = mt->num_samples;
- rb->Width = mt->logical_width0;
- rb->Height = mt->logical_height0;
+ /* Program takes care of msaa and mip-level access manually for stencil.
+ * The surface is also treated as Y-tiled instead of as W-tiled calling for
+ * twice the width and half the height in dimensions.
+ */
+ if (flat) {
+ static const unsigned halign_stencil = 8;
+
+ rb->NumSamples = 0;
+ rb->Width = ALIGN(mt->total_width, halign_stencil) * 2;
+ rb->Height = (mt->total_height / mt->physical_depth0) / 2;
+ irb->mt_level = 0;
+ } else {
+ rb->NumSamples = mt->num_samples;
+ rb->Width = mt->logical_width0;
+ rb->Height = mt->logical_height0;
+ irb->mt_level = level;
+ }
+
+ irb->mt_layer = layer;
intel_miptree_reference(&irb->mt, mt);
@@ -101,8 +119,8 @@ brw_meta_updownsample(struct brw_context *brw,
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(2, fbos);
- src_rbo = brw_get_rb_for_first_slice(brw, src_mt);
- dst_rbo = brw_get_rb_for_first_slice(brw, dst_mt);
+ src_rbo = brw_get_rb_for_slice(brw, src_mt, 0, 0, false);
+ dst_rbo = brw_get_rb_for_slice(brw, dst_mt, 0, 0, false);
src_fbo = fbos[0];
dst_fbo = fbos[1];
--
1.8.3.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
