On Sat, Feb 22, 2014 at 11:05:34AM +0200, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 28
> ++++++++++++++++++++++--
> 1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 6f23cec..2e841d9 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -194,12 +194,36 @@ const struct intel_mipmap_tree *
> brw_get_texture_surface(const struct gl_texture_object *tex_obj,
> struct brw_wm_surface *surface)
> {
> - const struct intel_texture_object *intel_tex =
> intel_texture_object(tex_obj);
> + const struct intel_texture_object *intel_tex =
> + (const struct intel_texture_object *)tex_obj;
This actually belongs to patch number 6, I merged it to the wrong patch when I
fixed compiler warning on intel_texture_object() needing non-constant pointer.
> const struct gl_texture_image *first =
> tex_obj->Image[0][tex_obj->BaseLevel];
> const struct intel_mipmap_tree *mt = intel_tex->mt;
>
> if (tex_obj->StencilSampling && first->_BaseFormat == GL_DEPTH_STENCIL) {
> - assert(!"Stencil indexing shouldn't be enabled yet");
> + const unsigned level = tex_obj->BaseLevel - mt->first_level;
> +
> + mt = mt->stencil_mt;
> +
> + /* Stencil is really W-tiled but as the hardware does not support
> + * sampling from it, it needs to be treated as Y-tiled with adjusted
> + * dimensions instead. Y-tiles are twice as wide and half as high as W.
> + * Also one needs to take into account that both tilings consist of
> + * 8x4 subtiles.
> + */
> + const unsigned x_align = 8, y_align = 4;
> +
> + surface->tiling = I915_TILING_Y;
> + surface->width = ALIGN(minify(mt->physical_width0, level), x_align) *
> 2;
> + surface->height = ALIGN(minify(mt->physical_height0, level), y_align)
> / 2;
> + surface->pitch = 2 * mt->region->pitch;
> + surface->min_lod = 0;
> + surface->mip_count = 0;
> + surface->depth = 1;
> +
> + /* Texture surfaces are always resolved to the layer zero. */
> + surface->page_offset = intel_miptree_get_tile_offsets(
> + mt, level, 0, true,
> + &surface->tile_x, &surface->tile_y);
> } else {
> surface->tiling = mt->region->tiling;
> surface->width = mt->logical_width0;
> --
> 1.8.3.1
>
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