On Die, 2013-12-03 at 21:33 +0100, Andreas Hartmetz wrote:
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c
> b/src/gallium/drivers/radeonsi/si_state.c
> index 24c9cf3..7b1a6df 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -1842,9 +1854,21 @@ static void si_db(struct r600_context *rctx, struct
> si_pm4_state *pm4,
> s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
> }
>
> + uint32_t db_htile_data_base = 0;
> + uint32_t db_htile_surface = 0;
> + /* use htile only for first level */
> + if (rtex->htile_buffer && !level) {
> + z_info |= S_028040_TILE_SURFACE_ENABLE(1);
> + uint64_t va = r600_resource_va(&rctx->screen->b.b,
> &rtex->htile_buffer->b.b);
> + db_htile_data_base = va >> 8;
> +
> + db_htile_surface = S_028ABC_FULL_CACHE(1);
> + }
> +
> si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
> S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
> S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
> + si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
>
> si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
> si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
> @@ -1858,6 +1882,8 @@ static void si_db(struct r600_context *rctx, struct
> si_pm4_state *pm4,
>
> si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE,
> S_028058_PITCH_TILE_MAX(pitch));
> si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE,
> S_02805C_SLICE_TILE_MAX(slice));
> +
> + si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
> }
Do the R_028014_DB_HTILE_DATA_BASE and R_028ABC_DB_HTILE_SURFACE
registers need to be written when S_028040_TILE_SURFACE_ENABLE is not
enabled in R_028040_DB_Z_INFO?
BTW, I agree with Alex about mixing code and declarations.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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