On Tue, Dec 3, 2013 at 3:33 PM, Andreas Hartmetz <ahartm...@gmail.com> wrote:
> ---
> src/gallium/drivers/radeonsi/si_state.c | 28 +++++++++++++++++++++++++++-
> 1 file changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c
> b/src/gallium/drivers/radeonsi/si_state.c
> index 24c9cf3..7b1a6df 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -757,7 +757,19 @@ static void *si_create_dsa_state(struct pipe_context
> *ctx,
> db_depth_control |= S_028800_Z_ENABLE(state->depth.enabled) |
> S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
> S_028800_ZFUNC(state->depth.func);
> - db_render_override |=
> S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
> +
> + struct r600_context *rctx = (struct r600_context *)ctx;
> + struct pipe_surface *surf = rctx->framebuffer.zsbuf;
> + struct r600_texture *rtex = 0;
Please don't mix code and declarations.
Alex
> + if (surf) {
> + rtex = (struct r600_texture*)surf->texture;
> + }
> + if (rtex && rtex->htile_buffer) {
> + /* Force off means no force, DB_SHADER_CONTROL decides */
> + db_render_override |=
> S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
> + } else {
> + db_render_override |=
> S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
> + }
>
> /* write remaining registers and return */
>
> @@ -1842,9 +1854,21 @@ static void si_db(struct r600_context *rctx, struct
> si_pm4_state *pm4,
> s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
> }
>
> + uint32_t db_htile_data_base = 0;
> + uint32_t db_htile_surface = 0;
> + /* use htile only for first level */
> + if (rtex->htile_buffer && !level) {
> + z_info |= S_028040_TILE_SURFACE_ENABLE(1);
> + uint64_t va = r600_resource_va(&rctx->screen->b.b,
> &rtex->htile_buffer->b.b);
> + db_htile_data_base = va >> 8;
> +
> + db_htile_surface = S_028ABC_FULL_CACHE(1);
> + }
> +
> si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
> S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
> S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
> + si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
>
> si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
> si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
> @@ -1858,6 +1882,8 @@ static void si_db(struct r600_context *rctx, struct
> si_pm4_state *pm4,
>
> si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE,
> S_028058_PITCH_TILE_MAX(pitch));
> si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE,
> S_02805C_SLICE_TILE_MAX(slice));
> +
> + si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
> }
>
> #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
> --
> 1.8.3.2
>
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