On Sat, Nov 16, 2013 at 3:53 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> On 11/16/2013 03:24 PM, Matt Turner wrote:
>> For commit 4df56177 Paul discovered that the hardware restriction that
>> Align16 instructions cannot be compressed was lifted on Haswell. This
>> has prevented us from emitting compressed three-source instructions.
>>
>> For added confirmation, the bspec lists a work around called
>> WaBreakSimd16TernaryInstructionsIntoSimd8 that hasn't been applicable
>> since very early Haswell silicon.
>> ---
>> Don't do it for BFI2 (see next patch).
>>
>> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> index 63ac530..1e5422c 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> @@ -1404,7 +1404,7 @@ fs_generator::generate_code(exec_list *instructions)
>> case BRW_OPCODE_MAD:
>> assert(brw->gen >= 6);
>> brw_set_access_mode(p, BRW_ALIGN_16);
>> - if (dispatch_width == 16) {
>> + if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
>> brw_set_compression_control(p, BRW_COMPRESSION_NONE);
>> brw_MAD(p, dst, src[0], src[1], src[2]);
>> brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
>> @@ -1419,7 +1419,7 @@ fs_generator::generate_code(exec_list *instructions)
>> case BRW_OPCODE_LRP:
>> assert(brw->gen >= 6);
>> brw_set_access_mode(p, BRW_ALIGN_16);
>> - if (dispatch_width == 16) {
>> + if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
>> brw_set_compression_control(p, BRW_COMPRESSION_NONE);
>> brw_LRP(p, dst, src[0], src[1], src[2]);
>> brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
>> @@ -1516,7 +1516,7 @@ fs_generator::generate_code(exec_list *instructions)
>> case BRW_OPCODE_BFE:
>> assert(brw->gen >= 7);
>> brw_set_access_mode(p, BRW_ALIGN_16);
>> - if (dispatch_width == 16) {
>> + if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
>> brw_set_compression_control(p, BRW_COMPRESSION_NONE);
>> brw_BFE(p, dst, src[0], src[1], src[2]);
>> brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
>>
>
> Ehhhhhh. These checks look wrong; won't they make us stop breaking
> these into two 8-wide halves on Sandybridge? MAD and LRP are supported
> there.
>
> I think you just want:
>
> if (dispatch_width == 16 && !brw->is_haswell) {
Yes. Silly mistake.
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