On 11/16/2013 03:24 PM, Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 1e5422c..bf38db6 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -1530,11 +1530,32 @@ fs_generator::generate_code(exec_list *instructions)
>
> case BRW_OPCODE_BFI1:
> assert(brw->gen >= 7);
> - brw_BFI1(p, dst, src[0], src[1]);
> + /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
> + * should
> + *
> + * "Force BFI instructions to be executed always in SIMD8."
> + */
> + if (dispatch_width == 16 && brw->is_haswell) {
> + brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_BFI1(p, dst, src[0], src[1]);
> + brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
> + brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + } else {
> + brw_BFI1(p, dst, src[0], src[1]);
> + }
> break;
> case BRW_OPCODE_BFI2:
> assert(brw->gen >= 7);
> brw_set_access_mode(p, BRW_ALIGN_16);
> + /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
> + * should
> + *
> + * "Force BFI instructions to be executed always in SIMD8."
> + *
> + * Otherwise we would be able to emit compressed instructions like
> we
> + * do for the other three-source instructions.
> + */
> if (dispatch_width == 16) {
> brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> brw_BFI2(p, dst, src[0], src[1], src[2]);
>
I'm skeptical that BFI needs to be broken in two on Haswell but not on
Ivybridge or Baytrail. I'd guess it just always needs to be broken down.
Is there some way I can test that for you?
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