Non-pipelined commands need this flush. Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index da523e5..ce215c2 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -957,6 +957,9 @@ void gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, const brw_blorp_params *params) { + if (brw->gen == 6) + intel_emit_post_sync_nonzero_flush(brw); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); OUT_BATCH(0); -- 1.8.3.2 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev