v2: Only lower bitfieldInsert to BFM+BFI (and don't lower
bitfieldExtract at all) since three-source instructions are now
usable in the vertex shader.
v3: Lower bitfield_insert in the same pass with everything else, since
it doesn't produce any instructions to be lowered (the other two
lowering passes that were in a previous iteration of this series
emitted subtractions which needed to be lowered).
Reviewed-by: Chris Forbes <chr...@ijw.co.nz> [v2]
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 5addff6..283e4a8 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -152,6 +152,9 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
*/
brw_lower_packing_builtins(brw, (gl_shader_type) stage, shader->ir);
do_mat_op_to_vec(shader->ir);
+ const int bitfield_insert = intel->gen >= 7
+ ? BITFIELD_INSERT_TO_BFM_BFI
+ : 0;
const int lrp_to_arith = intel->gen < 6 ? LRP_TO_ARITH : 0;
lower_instructions(shader->ir,
MOD_TO_FRACT |
@@ -159,6 +162,7 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
SUB_TO_ADD_NEG |
EXP_TO_EXP2 |
LOG_TO_LOG2 |
+ bitfield_insert |
lrp_to_arith);
/* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
--
1.8.1.5
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