You should also bump R600_NUM_ATOMS whenever you add a new atom with
r600_init_atom. BTW, what does LS stand for?
Marek
On Tue, Apr 23, 2013 at 5:24 AM, Tom Stellard <t...@stellard.net> wrote:
> From: Tom Stellard <thomas.stell...@amd.com>
>
> ---
> src/gallium/drivers/r600/evergreen_state.c | 34
> +++++++++++++++++++++---------
> src/gallium/drivers/r600/evergreend.h | 2 ++
> src/gallium/drivers/r600/r600_pipe.h | 9 ++++++++
> 3 files changed, 35 insertions(+), 10 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_state.c
> b/src/gallium/drivers/r600/evergreen_state.c
> index d2a2008..ba9e736 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -2473,7 +2473,8 @@ static void evergreen_emit_constant_buffers(struct
> r600_context *rctx,
> struct r600_constbuf_state *state,
> unsigned buffer_id_base,
> unsigned reg_alu_constbuf_size,
> - unsigned reg_alu_const_cache)
> + unsigned reg_alu_const_cache,
> + unsigned pkt_flags)
> {
> struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
> uint32_t dirty_mask = state->dirty_mask;
> @@ -2491,14 +2492,15 @@ static void evergreen_emit_constant_buffers(struct
> r600_context *rctx,
> va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
> va += cb->buffer_offset;
>
> - r600_write_context_reg(cs, reg_alu_constbuf_size +
> buffer_index * 4,
> - ALIGN_DIVUP(cb->buffer_size >> 4, 16));
> - r600_write_context_reg(cs, reg_alu_const_cache + buffer_index
> * 4, va >> 8);
> + r600_write_context_reg_flag(cs, reg_alu_constbuf_size +
> buffer_index * 4,
> + ALIGN_DIVUP(cb->buffer_size >> 4, 16),
> pkt_flags);
> + r600_write_context_reg_flag(cs, reg_alu_const_cache +
> buffer_index * 4, va >> 8,
> + pkt_flags);
>
> - r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
> + r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
> r600_write_value(cs, r600_context_bo_reloc(rctx,
> &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
>
> - r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
> + r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) |
> pkt_flags);
> r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
> r600_write_value(cs, va); /* RESOURCEi_WORD0 */
> r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset -
> 1); /* RESOURCEi_WORD1 */
> @@ -2516,7 +2518,7 @@ static void evergreen_emit_constant_buffers(struct
> r600_context *rctx,
> r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
> r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
>
> - r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
> + r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
> r600_write_value(cs, r600_context_bo_reloc(rctx,
> &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
>
> dirty_mask &= ~(1 << buffer_index);
> @@ -2528,21 +2530,32 @@ static void evergreen_emit_vs_constant_buffers(struct
> r600_context *rctx, struct
> {
> evergreen_emit_constant_buffers(rctx,
> &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
> R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
> - R_028980_ALU_CONST_CACHE_VS_0);
> + R_028980_ALU_CONST_CACHE_VS_0,
> + 0 /* PKT3 flags */);
> }
>
> static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx,
> struct r600_atom *atom)
> {
> evergreen_emit_constant_buffers(rctx,
> &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
> R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
> - R_0289C0_ALU_CONST_CACHE_GS_0);
> + R_0289C0_ALU_CONST_CACHE_GS_0,
> + 0 /* PKT3 flags */);
> }
>
> static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx,
> struct r600_atom *atom)
> {
> evergreen_emit_constant_buffers(rctx,
> &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
> R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
> - R_028940_ALU_CONST_CACHE_PS_0);
> + R_028940_ALU_CONST_CACHE_PS_0,
> + 0 /* PKT3 flags */);
> +}
> +
> +static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx,
> struct r600_atom *atom)
> +{
> + evergreen_emit_constant_buffers(rctx,
> &rctx->constbuf_state[PIPE_SHADER_COMPUTE], 816,
> + R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
> + R_028F40_ALU_CONST_CACHE_LS_0,
> + RADEON_CP_PACKET3_COMPUTE_MODE);
> }
>
> static void evergreen_emit_sampler_views(struct r600_context *rctx,
> @@ -3802,6 +3815,7 @@ void evergreen_init_state_functions(struct r600_context
> *rctx)
> r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom,
> id++, evergreen_emit_vs_constant_buffers, 0);
> r600_init_atom(rctx,
> &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++,
> evergreen_emit_gs_constant_buffers, 0);
> r600_init_atom(rctx,
> &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++,
> evergreen_emit_ps_constant_buffers, 0);
> + r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom,
> id++, evergreen_emit_cs_constant_buffers, 0);
> /* shader program */
> r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++,
> evergreen_emit_cs_shader, 0);
> /* sampler */
> diff --git a/src/gallium/drivers/r600/evergreend.h
> b/src/gallium/drivers/r600/evergreend.h
> index 53b68a4..92ca1ab 100644
> --- a/src/gallium/drivers/r600/evergreend.h
> +++ b/src/gallium/drivers/r600/evergreend.h
> @@ -1661,6 +1661,7 @@
> #define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180
> #define R_028184_ALU_CONST_BUFFER_SIZE_VS_1 0x00028184
> #define R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0 0x000281C0
> +#define R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0 0x00028FC0
> #define R_028200_PA_SC_WINDOW_OFFSET 0x00028200
> #define R_02820C_PA_SC_CLIPRECT_RULE 0x0002820C
> #define R_028210_PA_SC_CLIPRECT_0_TL 0x00028210
> @@ -1852,6 +1853,7 @@
> #define R_028980_ALU_CONST_CACHE_VS_0 0x00028980
> #define R_028984_ALU_CONST_CACHE_VS_1 0x00028984
> #define R_0289C0_ALU_CONST_CACHE_GS_0 0x000289C0
> +#define R_028F40_ALU_CONST_CACHE_LS_0 0x00028F40
> #define R_028A04_PA_SU_POINT_MINMAX 0x00028A04
> #define S_028A04_MIN_SIZE(x) (((x) & 0xFFFF) << 0)
> #define G_028A04_MIN_SIZE(x) (((x) >> 0) & 0xFFFF)
> diff --git a/src/gallium/drivers/r600/r600_pipe.h
> b/src/gallium/drivers/r600/r600_pipe.h
> index 4a692e7..b910677 100644
> --- a/src/gallium/drivers/r600/r600_pipe.h
> +++ b/src/gallium/drivers/r600/r600_pipe.h
> @@ -1110,6 +1110,15 @@ static INLINE void
> r600_write_compute_context_reg(struct radeon_winsys_cs *cs, u
> r600_write_value(cs, value);
> }
>
> +static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs,
> unsigned reg, unsigned value, unsigned flag)
> +{
> + if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
> + r600_write_compute_context_reg(cs, reg, value);
> + } else {
> + r600_write_context_reg(cs, reg, value);
> + }
> +
> +}
> static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs,
> unsigned reg, unsigned value)
> {
> r600_write_ctl_const_seq(cs, reg, 1);
> --
> 1.7.11.4
>
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