This series lives on my gles3-glsl-packing branch.
I tested this series against my piglit gles3-glsl-packing branch on Ivybridge
and Sandybridge. No regressions relative to the Mesa gles3-d72ba278e.
v2:
- Do all of idr's minor fixes.
- Improve the rounding bias in _mesa_float_to_half.
- For evaluating constant pack/unpackHalf2x16 expressions, use
_mesa_float_to_half/_mesa_half_to_float [for idr].
- Add a bunch of new stuff to ir_builder.
- Rewrite the lowering pass using ir_builder [for idr].
- In lowering packHalf2x16, don't truncate subnormal float16 values to zero.
And round to even rather than to zero. [for stereotype441]
Chad Versace (20):
glsl: Fix typo in comment
glsl: Add IR lisp for GLSL ES 3.00 pack/unpack functions
glsl: Extend ir_expression_operation for GLSL 3.00 pack/unpack
functions (v2)
glsl/standalone_scaffolding: Add stub for _mesa_warning()
mesa,glsl: Move round_to_even() from glsl to mesa/main
mesa: Remove rounding bias in _mesa_float_to_half()
glsl: Evaluate constant GLSL ES 3.00 pack/unpack expressions (v2)
glsl/ir_factory: Initialize members to NULL in constructor
glsl/ir_builder: Add more helpers for constructing expressions
glsl/ir_factory: Add helper method for making an ir_constant
glsl/ir_builder: Add `enum writemask`
glsl/ir_builder: Add helpers for making if-statements
glsl: Reformat and/or/xor cases in ir_expression ctor
glsl: Fix type-deduction for and/or/xor expressions
glsl: Add lowering pass for GLSL ES 3.00 pack/unpack operations (v2)
i965: Lower the GLSL ES 3.00 pack/unpack operations (v2)
i965: Add opcodes for F32TO16 and F16TO32
i965: Quote the PRM on a HorzStride subtlety
i965/vs/gen7: Emit code for GLSL ES 3.00 pack/unpack operations
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v2)
src/glsl/Makefile.am | 2 +
src/glsl/Makefile.sources | 1 +
src/glsl/builtin_compiler/Makefile.am | 1 +
src/glsl/builtins/ir/packHalf2x16.ir | 6 +
src/glsl/builtins/ir/packSnorm2x16.ir | 6 +
src/glsl/builtins/ir/packUnorm2x16.ir | 6 +
src/glsl/builtins/ir/unpackHalf2x16.ir | 6 +
src/glsl/builtins/ir/unpackSnorm2x16.ir | 6 +
src/glsl/builtins/ir/unpackUnorm2x16.ir | 6 +
src/glsl/builtins/profiles/300es.glsl | 14 +-
src/glsl/ir.cpp | 36 +-
src/glsl/ir.h | 33 +-
src/glsl/ir_builder.cpp | 159 +++
src/glsl/ir_builder.h | 72 ++
src/glsl/ir_constant_expression.cpp | 208 +++-
src/glsl/ir_optimization.h | 20 +
src/glsl/ir_validate.cpp | 26 +
src/glsl/lower_packing_builtins.cpp | 1043 ++++++++++++++++++++
src/glsl/standalone_scaffolding.cpp | 18 +
src/glsl/standalone_scaffolding.h | 3 +
src/mesa/drivers/dri/i965/brw_defines.h | 3 +
src/mesa/drivers/dri/i965/brw_disasm.c | 2 +
src/mesa/drivers/dri/i965/brw_eu.h | 2 +
src/mesa/drivers/dri/i965/brw_eu_emit.c | 7 +-
src/mesa/drivers/dri/i965/brw_fs.h | 7 +
.../dri/i965/brw_fs_channel_expressions.cpp | 12 +
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 39 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 82 +-
src/mesa/drivers/dri/i965/brw_shader.cpp | 32 +
src/mesa/drivers/dri/i965/brw_vec4.h | 3 +
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 8 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 155 +++
src/mesa/main/imports.c | 86 +-
src/mesa/main/imports.h | 3 +
src/mesa/program/ir_to_mesa.cpp | 12 +-
35 files changed, 2061 insertions(+), 64 deletions(-)
create mode 100644 src/glsl/builtins/ir/packHalf2x16.ir
create mode 100644 src/glsl/builtins/ir/packSnorm2x16.ir
create mode 100644 src/glsl/builtins/ir/packUnorm2x16.ir
create mode 100644 src/glsl/builtins/ir/unpackHalf2x16.ir
create mode 100644 src/glsl/builtins/ir/unpackSnorm2x16.ir
create mode 100644 src/glsl/builtins/ir/unpackUnorm2x16.ir
create mode 100644 src/glsl/lower_packing_builtins.cpp
--
1.8.1.1
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