---
lib/Target/AMDGPU/R600Defines.h | 4 ++--
lib/Target/AMDGPU/R600Instructions.td | 11 +++++++----
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/lib/Target/AMDGPU/R600Defines.h b/lib/Target/AMDGPU/R600Defines.h
index 8191c6a..ca8fdf5 100644
--- a/lib/Target/AMDGPU/R600Defines.h
+++ b/lib/Target/AMDGPU/R600Defines.h
@@ -23,7 +23,7 @@
// Helper for finding getting the operand index for the instruction flags
// operand.
-#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
+#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x7)
namespace R600_InstFlag {
enum TIF {
@@ -34,7 +34,7 @@ namespace R600_InstFlag {
TRIG = (1 << 4),
OP3 = (1 << 5),
VECTOR = (1 << 6)
- //FlagOperand bits 7, 8
+ //FlagOperand bits 7, 8, 9
};
}
diff --git a/lib/Target/AMDGPU/R600Instructions.td
b/lib/Target/AMDGPU/R600Instructions.td
index 45b6b10..da32329 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -21,7 +21,7 @@ class InstR600 <bits<11> inst, dag outs, dag ins, string asm,
list<dag> pattern,
bit Trig = 0;
bit Op3 = 0;
bit isVector = 0;
- bits<2> FlagOperandIdx = 0;
+ bits<3> FlagOperandIdx = 0;
bits<11> op_code = inst;
//let Inst = inst;
@@ -38,7 +38,7 @@ class InstR600 <bits<11> inst, dag outs, dag ins, string asm,
list<dag> pattern,
// Vector instructions are instructions that must fill all slots in an
// instruction group
let TSFlags{6} = isVector;
- let TSFlags{8-7} = FlagOperandIdx;
+ let TSFlags{9-7} = FlagOperandIdx;
}
class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
@@ -77,6 +77,7 @@ class R600_ALU {
def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
(ops PRED_SEL_OFF)>;
+def Flag : OptionalDefOperand<i32, (ops imm),( ops (i32 0))>;
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
@@ -84,7 +85,7 @@ class R600_1OP <bits<11> inst, string opName, list<dag>
pattern,
InstrItinClass itin = AnyALU> :
InstR600 <inst,
(outs R600_Reg32:$dst),
- (ins R600_Reg32:$src, R600_Pred:$p, variable_ops),
+ (ins R600_Reg32:$src, R600_Pred:$p, Flag:$flag, variable_ops),
!strconcat(opName, " $dst, $src $p"),
pattern,
itin>{
@@ -93,13 +94,14 @@ class R600_1OP <bits<11> inst, string opName, list<dag>
pattern,
let Inst{8-0} = src;
let Inst{49-39} = inst;
let Inst{59-53} = dst;
+ let FlagOperandIdx = 3;
}
class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
InstrItinClass itin = AnyALU> :
InstR600 <inst,
(outs R600_Reg32:$dst),
- (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops),
+ (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, Flag:$flag,
variable_ops),
!strconcat(opName, " $dst, $src0, $src1"),
pattern,
itin>{
@@ -110,6 +112,7 @@ class R600_2OP <bits<11> inst, string opName, list<dag>
pattern,
let Inst{21-13} = src1;
let Inst{49-39} = inst;
let Inst{59-53} = dst;
+ let FlagOperandIdx = 4;
}
class R600_3OP <bits<11> inst, string opName, list<dag> pattern,
--
1.7.11.7
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